gpu: nvgpu: gv11b: enable and handle mpc exception

Implement gr ops to handle MPC exception triggered per TPC

JIRA GPUT19X-69

Change-Id: Ia92b1d51ad896116b25d71e07ed26f1539475be8
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1515915
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>

1 files changed, 32 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
index 051961d2..53dc7c87 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
@@ -902,6 +902,22 @@ static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f(void)
 {
         return 0x2;
 }
+static inline u32 gr_gpc0_tpc0_mpc_hww_esr_r(void)
+{
+        return 0x00504430;
+}
+static inline u32 gr_gpc0_tpc0_mpc_hww_esr_reset_trigger_f(void)
+{
+        return 0x40000000;
+}
+static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_r(void)
+{
+        return 0x00504434;
+}
+static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_veid_v(u32 r)
+{
+        return (r >> 0) & 0x3f;
+}
 static inline u32 gr_pri_be0_crop_status1_r(void)
 {
         return 0x00410134;
@@ -3470,6 +3486,10 @@ static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void)
 {
         return 0x1;
 }
+static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_mpc_enabled_f(void)
+{
+        return 0x10;
+}
 static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void)
 {
         return 0x0050450c;
@@ -3482,6 +3502,10 @@ static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void)
 {
         return 0x2;
 }
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_mpc_enabled_f(void)
+{
+        return 0x10;
+}
 static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void)
 {
         return 0x0041ac94;
@@ -3618,6 +3642,14 @@ static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void)
 {
         return 0x00000001;
 }
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m(void)
+{
+        return 0x1 << 4;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_pending_f(void)
+{
+        return 0x10;
+}
 static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_r(void)
 {
         return 0x00504704;