gpu: nvgpu: gv11b: enable more gr exceptions

-pd, scc, ds, ssync, mme and sked exceptions are
 enabled. This will be useful for debugging
-Handle enabled interrupts
-Add gr ops to handle ssync hww. For legacy
 chips, ssync hww_esr register is gpcs_ppcs_ssync_hww_esr.
 Since ssync hww is not enabled on legacy chips, added
 ssync hww exception handling for volta only.

Change-Id: I63ba2eb51fa82e74832df26ee4cf3546458e5669
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1644751
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 76 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
index a4bcce42..d34dcf33 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
@@ -184,6 +184,22 @@ static inline u32 gr_exception_sked_m(void)
 {
         return 0x1U << 8U;
 }
+static inline u32 gr_exception_pd_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 gr_exception_scc_m(void)
+{
+        return 0x1U << 3U;
+}
+static inline u32 gr_exception_ssync_m(void)
+{
+        return 0x1U << 5U;
+}
+static inline u32 gr_exception_mme_m(void)
+{
+        return 0x1U << 7U;
+}
 static inline u32 gr_exception1_r(void)
 {
         return 0x00400118U;
@@ -232,6 +248,46 @@ static inline u32 gr_exception_en_ds_enabled_f(void)
 {
         return 0x10U;
 }
+static inline u32 gr_exception_en_pd_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 gr_exception_en_pd_enabled_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gr_exception_en_scc_m(void)
+{
+        return 0x1U << 3U;
+}
+static inline u32 gr_exception_en_scc_enabled_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gr_exception_en_ssync_m(void)
+{
+        return 0x1U << 5U;
+}
+static inline u32 gr_exception_en_ssync_enabled_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_exception_en_mme_m(void)
+{
+        return 0x1U << 7U;
+}
+static inline u32 gr_exception_en_mme_enabled_f(void)
+{
+        return 0x80U;
+}
+static inline u32 gr_exception_en_sked_m(void)
+{
+        return 0x1U << 8U;
+}
+static inline u32 gr_exception_en_sked_enabled_f(void)
+{
+        return 0x100U;
+}
 static inline u32 gr_exception1_en_r(void)
 {
         return 0x00400130U;
@@ -1408,6 +1464,10 @@ static inline u32 gr_fe_hww_esr_en_enable_f(void)
 {
         return 0x80000000U;
 }
+static inline u32 gr_fe_hww_esr_info_r(void)
+{
+        return 0x004041b0U;
+}
 static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(void)
 {
         return 0x00419eacU;
@@ -1536,6 +1596,10 @@ static inline u32 gr_mme_hww_esr_en_enable_f(void)
 {
         return 0x80000000U;
 }
+static inline u32 gr_mme_hww_esr_info_r(void)
+{
+        return 0x00404494U;
+}
 static inline u32 gr_memfmt_hww_esr_r(void)
 {
         return 0x00404600U;
@@ -2980,6 +3044,18 @@ static inline u32 gr_scc_hww_esr_en_enable_f(void)
 {
         return 0x80000000U;
 }
+static inline u32 gr_ssync_hww_esr_r(void)
+{
+        return 0x00405a14U;
+}
+static inline u32 gr_ssync_hww_esr_reset_active_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_ssync_hww_esr_en_enable_f(void)
+{
+        return 0x80000000U;
+}
 static inline u32 gr_sked_hww_esr_r(void)
 {
         return 0x00407020U;