gpu: nvgpu: gv11b: init enable_exceptions gr ops

Enable FE, MEMFMT, DS and GPC exceptions only.
Make sure corresponding HWW_ESR are enabled too.

JIRA GPUT19X-75

Change-Id: Icf47b7e531dd72b59cbc6ac54b5902187f703d61
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1474859
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 28 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
index 9917f86d..2d5afb29 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
@@ -194,6 +194,34 @@ static inline u32 gr_exception_en_fe_m(void)
 {
         return 0x1 << 0;
 }
+static inline u32 gr_exception_en_fe_enabled_f(void)
+{
+        return 0x1;
+}
+static inline u32 gr_exception_en_gpc_m(void)
+{
+        return 0x1 << 24;
+}
+static inline u32 gr_exception_en_gpc_enabled_f(void)
+{
+        return 0x1000000;
+}
+static inline u32 gr_exception_en_memfmt_m(void)
+{
+        return 0x1 << 1;
+}
+static inline u32 gr_exception_en_memfmt_enabled_f(void)
+{
+        return 0x2;
+}
+static inline u32 gr_exception_en_ds_m(void)
+{
+        return 0x1 << 4;
+}
+static inline u32 gr_exception_en_ds_enabled_f(void)
+{
+        return 0x10;
+}
 static inline u32 gr_exception1_en_r(void)
 {
         return 0x00400130;