gpu: nvgpu: gv11b: scrub more fileds for sm l1 tag

SM L1 tag needs to scrub for following additional fields:
sm_l1_tag_ecc_control_scrub_pixprf
sm_l1_tag_ecc_control_scrub_miss_fifo

With this SM L1 TAG DBE errors after railgate/ungate
are fixed.

Bug 2039629

Change-Id: I10ce1d1dd28102f4c2f3fe2fe81801db67b76a21
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1626748
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 32 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
index 29999163..1e82456f 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
@@ -1112,6 +1112,22 @@ static inline u32 gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_el1_1_task_f(void
 {
         return 0x2U;
 }
+static inline u32 gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_pixprf_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_pixprf_task_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_miss_fifo_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_miss_fifo_task_f(void)
+{
+        return 0x20U;
+}
 static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_r(void)
 {
         return 0x00504620U;
@@ -1132,6 +1148,22 @@ static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_el1_1_init_f(void
 {
         return 0x0U;
 }
+static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_pixprf_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_pixprf_init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_miss_fifo_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_miss_fifo_init_f(void)
+{
+        return 0x0U;
+}
 static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_r(void)
 {
         return 0x00419e34U;