gpu: nvgpu: gv11b: Add L1 DATA + iCACHE parity

This CL covers the following parity support (uncorrected error),
1) SM's L1 DATA
2) SM's L0 && L1 icache

Volta Resiliency Id - Volta-634

JIRA GPUT19X-113
JIRA GPUT19X-99

Bug 1807553

Change-Id: Iacbf492028983529dadc5753007e43510b8cb786
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1483681
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 128 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
index 4b2e8c32..4ce69743 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
@@ -582,6 +582,134 @@ static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_v(u32
 {
         return (r >> 0) & 0xffff;
 }
+static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_r(void)
+{
+        return 0x0050436c;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_0_m(void)
+{
+        return 0x1 << 0;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_1_m(void)
+{
+        return 0x1 << 1;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_0_m(void)
+{
+        return 0x1 << 2;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_1_m(void)
+{
+        return 0x1 << 3;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_total_counter_overflow_v(u32 r)
+{
+        return (r >> 8) & 0x1;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r)
+{
+        return (r >> 10) & 0x1;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_reset_task_f(void)
+{
+        return 0x40000000;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_r(void)
+{
+        return 0x00504370;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_s(void)
+{
+        return 16;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_v(u32 r)
+{
+        return (r >> 0) & 0xffff;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_r(void)
+{
+        return 0x00504374;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_s(void)
+{
+        return 16;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_v(u32 r)
+{
+        return (r >> 0) & 0xffff;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_r(void)
+{
+        return 0x0050464c;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l0_data_m(void)
+{
+        return 0x1 << 0;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l0_predecode_m(void)
+{
+        return 0x1 << 1;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l1_data_m(void)
+{
+        return 0x1 << 2;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l1_predecode_m(void)
+{
+        return 0x1 << 3;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l0_data_m(void)
+{
+        return 0x1 << 4;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l0_predecode_m(void)
+{
+        return 0x1 << 5;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l1_data_m(void)
+{
+        return 0x1 << 6;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l1_predecode_m(void)
+{
+        return 0x1 << 7;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_total_counter_overflow_v(u32 r)
+{
+        return (r >> 16) & 0x1;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r)
+{
+        return (r >> 18) & 0x1;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_reset_task_f(void)
+{
+        return 0x40000000;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_r(void)
+{
+        return 0x00504650;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_total_s(void)
+{
+        return 16;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_total_v(u32 r)
+{
+        return (r >> 0) & 0xffff;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_r(void)
+{
+        return 0x00504654;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_total_s(void)
+{
+        return 16;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_total_v(u32 r)
+{
+        return (r >> 0) & 0xffff;
+}
 static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_r(void)
 {
         return 0x00504624;