gpu: nvgpu: gv11b: sw method for NVC397_SET_TEX_IN_DBG

Added sw method for NVC397_SET_TEX_IN_DBG with
following data fields:
data:0 PRI_TEX_IN_DBG_TSL1_RVCH_INVALIDATE
data:1 PRI_SM_L1TAG_CTRL_CACHE_SURFACE_LD
data:2 PRI_SM_L1TAG_CTRL_CACHE_SURFACE_ST

Bug 1934197

Change-Id: I0956d3f5c859ac23e16fb6b7372acd098dfb6d16
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master/r/1507479
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Wei Sun <wsun@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 32 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
index 29a8b33c..75a64be5 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
@@ -3830,6 +3830,38 @@ static inline u32 gr_zcull_subregion_qty_v(void)
 {
         return 0x00000010;
 }
+static inline u32 gr_gpcs_tpcs_tex_in_dbg_r(void)
+{
+        return 0x00419a00;
+}
+static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_f(u32 v)
+{
+        return (v & 0x1) << 19;
+}
+static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_m(void)
+{
+        return 0x1 << 19;
+}
+static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_r(void)
+{
+        return 0x00419bf0;
+}
+static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_f(u32 v)
+{
+        return (v & 0x1) << 5;
+}
+static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_m(void)
+{
+        return 0x1 << 5;
+}
+static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_f(u32 v)
+{
+        return (v & 0x1) << 10;
+}
+static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m(void)
+{
+        return 0x1 << 10;
+}
 static inline u32 gr_fe_pwr_mode_r(void)
 {
         return 0x00404170;