gpu: nvgpu: gv11b: disable SWDX spill buffer invalidates

Disable SWDX spill buffer invalidates as is required by HW. Since this
register is context-switched, add these in the GR init sequence.

Bug 2040262

Change-Id: I0be10d12516bce6ce6f8fb0e8af5b67f8af92257
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1650563
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 16 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
index c430122d..4458265d 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
@@ -3840,6 +3840,22 @@ static inline u32 gr_gpcs_swdx_dss_zbc_s_01_to_04_format_r(void)
 {
         return 0x00418198U;
 }
+static inline u32 gr_gpcs_swdx_spill_unit_r(void)
+{
+        return 0x00418e9cU;
+}
+static inline u32 gr_gpcs_swdx_spill_unit_spill_buffer_cache_mgmt_mode_m(void)
+{
+        return 0x1U << 16U;
+}
+static inline u32 gr_gpcs_swdx_spill_unit_spill_buffer_cache_mgmt_mode_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpcs_swdx_spill_unit_spill_buffer_cache_mgmt_mode_enabled_f(void)
+{
+        return 0x10000U;
+}
 static inline u32 gr_gpcs_setup_attrib_cb_base_r(void)
 {
         return 0x00418810U;