gpu: nvgpu: gv11b: disable SCC pagepool invalidates

Disable SCC pagepool invalidates as is required by HW. Since this
register is context-switched, add these in the GR init sequence.

Bug 2040262

Change-Id: I8dd1b7c7c4b0544878ca57b1261f9c85fa380d47
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1649719
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 16 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
index d34dcf33..c430122d 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
@@ -2932,6 +2932,22 @@ static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i)
 {
         return 0x00405870U + i*4U;
 }
+static inline u32 gr_scc_debug_r(void)
+{
+        return 0x00408000U;
+}
+static inline u32 gr_scc_debug_pagepool_invalidates_m(void)
+{
+        return 0x1U << 9U;
+}
+static inline u32 gr_scc_debug_pagepool_invalidates_disable_f(void)
+{
+        return 0x200U;
+}
+static inline u32 gr_scc_debug_pagepool_invalidates_enable_f(void)
+{
+        return 0x0U;
+}
 static inline u32 gr_scc_bundle_cb_base_r(void)
 {
         return 0x00408004U;