gpu: nvgpu: gv11b: generated mmu fault fields/masks

Generated h/w header for mmu fault handling

JIRA GPUT19X-7
JIRA GPUT19X-12

Change-Id: I857ab6b67f6d9ac9a2c2ee982496dd0603bd010e
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1494842
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit

1 files changed, 8 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h
index 22ad23bc..383f7773 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h
@@ -1274,6 +1274,10 @@ static inline u32 gmmu_fault_mmu_eng_id_physical_v(void)
 {
         return 0x0000001f;
 }
+static inline u32 gmmu_fault_mmu_eng_id_ce0_v(void)
+{
+        return 0x0000000f;
+}
 static inline u32 gmmu_fault_buf_size_v(void)
 {
         return 0x00000020;
@@ -1458,6 +1462,10 @@ static inline u32 gmmu_fault_buf_entry_replayable_fault_en_true_f(void)
 {
         return 0x40000000;
 }
+static inline u32 gmmu_fault_buf_entry_valid_m(void)
+{
+        return 0x1 << 31;
+}
 static inline u32 gmmu_fault_buf_entry_valid_v(u32 r)
 {
         return (r >> 31) & 0x1;