diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2017-09-25 16:33:12 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-09-27 17:17:51 -0400 |
commit | 406b73e422b6d31979b7ce0a0848a6c2025d7ebf (patch) | |
tree | cd0a3fa1e0d89ac5c54f4818540b4eb540440f26 /drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h | |
parent | e7c9109f60e2d5f5570f5e3c71dcc824bb415688 (diff) |
gpu: nvgpu: gp10b: Qualify unsigned HW constants
Re-generate hardware headers so that all unsigned constants are
qualified with postfix U. This removes the need for compiler to do
implicit signed->unsigned conversions.
Change-Id: I33d46bb103d083316266eb1d325ca9f1525bf047
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1567985
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h')
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h | 386 |
1 files changed, 193 insertions, 193 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h index c47a5de6..73a5c45c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h | |||
@@ -58,774 +58,774 @@ | |||
58 | 58 | ||
59 | static inline u32 pwr_falcon_irqsset_r(void) | 59 | static inline u32 pwr_falcon_irqsset_r(void) |
60 | { | 60 | { |
61 | return 0x0010a000; | 61 | return 0x0010a000U; |
62 | } | 62 | } |
63 | static inline u32 pwr_falcon_irqsset_swgen0_set_f(void) | 63 | static inline u32 pwr_falcon_irqsset_swgen0_set_f(void) |
64 | { | 64 | { |
65 | return 0x40; | 65 | return 0x40U; |
66 | } | 66 | } |
67 | static inline u32 pwr_falcon_irqsclr_r(void) | 67 | static inline u32 pwr_falcon_irqsclr_r(void) |
68 | { | 68 | { |
69 | return 0x0010a004; | 69 | return 0x0010a004U; |
70 | } | 70 | } |
71 | static inline u32 pwr_falcon_irqstat_r(void) | 71 | static inline u32 pwr_falcon_irqstat_r(void) |
72 | { | 72 | { |
73 | return 0x0010a008; | 73 | return 0x0010a008U; |
74 | } | 74 | } |
75 | static inline u32 pwr_falcon_irqstat_halt_true_f(void) | 75 | static inline u32 pwr_falcon_irqstat_halt_true_f(void) |
76 | { | 76 | { |
77 | return 0x10; | 77 | return 0x10U; |
78 | } | 78 | } |
79 | static inline u32 pwr_falcon_irqstat_exterr_true_f(void) | 79 | static inline u32 pwr_falcon_irqstat_exterr_true_f(void) |
80 | { | 80 | { |
81 | return 0x20; | 81 | return 0x20U; |
82 | } | 82 | } |
83 | static inline u32 pwr_falcon_irqstat_swgen0_true_f(void) | 83 | static inline u32 pwr_falcon_irqstat_swgen0_true_f(void) |
84 | { | 84 | { |
85 | return 0x40; | 85 | return 0x40U; |
86 | } | 86 | } |
87 | static inline u32 pwr_falcon_irqmode_r(void) | 87 | static inline u32 pwr_falcon_irqmode_r(void) |
88 | { | 88 | { |
89 | return 0x0010a00c; | 89 | return 0x0010a00cU; |
90 | } | 90 | } |
91 | static inline u32 pwr_falcon_irqmset_r(void) | 91 | static inline u32 pwr_falcon_irqmset_r(void) |
92 | { | 92 | { |
93 | return 0x0010a010; | 93 | return 0x0010a010U; |
94 | } | 94 | } |
95 | static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v) | 95 | static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v) |
96 | { | 96 | { |
97 | return (v & 0x1) << 0; | 97 | return (v & 0x1U) << 0U; |
98 | } | 98 | } |
99 | static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v) | 99 | static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v) |
100 | { | 100 | { |
101 | return (v & 0x1) << 1; | 101 | return (v & 0x1U) << 1U; |
102 | } | 102 | } |
103 | static inline u32 pwr_falcon_irqmset_mthd_f(u32 v) | 103 | static inline u32 pwr_falcon_irqmset_mthd_f(u32 v) |
104 | { | 104 | { |
105 | return (v & 0x1) << 2; | 105 | return (v & 0x1U) << 2U; |
106 | } | 106 | } |
107 | static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v) | 107 | static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v) |
108 | { | 108 | { |
109 | return (v & 0x1) << 3; | 109 | return (v & 0x1U) << 3U; |
110 | } | 110 | } |
111 | static inline u32 pwr_falcon_irqmset_halt_f(u32 v) | 111 | static inline u32 pwr_falcon_irqmset_halt_f(u32 v) |
112 | { | 112 | { |
113 | return (v & 0x1) << 4; | 113 | return (v & 0x1U) << 4U; |
114 | } | 114 | } |
115 | static inline u32 pwr_falcon_irqmset_exterr_f(u32 v) | 115 | static inline u32 pwr_falcon_irqmset_exterr_f(u32 v) |
116 | { | 116 | { |
117 | return (v & 0x1) << 5; | 117 | return (v & 0x1U) << 5U; |
118 | } | 118 | } |
119 | static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v) | 119 | static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v) |
120 | { | 120 | { |
121 | return (v & 0x1) << 6; | 121 | return (v & 0x1U) << 6U; |
122 | } | 122 | } |
123 | static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v) | 123 | static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v) |
124 | { | 124 | { |
125 | return (v & 0x1) << 7; | 125 | return (v & 0x1U) << 7U; |
126 | } | 126 | } |
127 | static inline u32 pwr_falcon_irqmclr_r(void) | 127 | static inline u32 pwr_falcon_irqmclr_r(void) |
128 | { | 128 | { |
129 | return 0x0010a014; | 129 | return 0x0010a014U; |
130 | } | 130 | } |
131 | static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v) | 131 | static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v) |
132 | { | 132 | { |
133 | return (v & 0x1) << 0; | 133 | return (v & 0x1U) << 0U; |
134 | } | 134 | } |
135 | static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v) | 135 | static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v) |
136 | { | 136 | { |
137 | return (v & 0x1) << 1; | 137 | return (v & 0x1U) << 1U; |
138 | } | 138 | } |
139 | static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v) | 139 | static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v) |
140 | { | 140 | { |
141 | return (v & 0x1) << 2; | 141 | return (v & 0x1U) << 2U; |
142 | } | 142 | } |
143 | static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v) | 143 | static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v) |
144 | { | 144 | { |
145 | return (v & 0x1) << 3; | 145 | return (v & 0x1U) << 3U; |
146 | } | 146 | } |
147 | static inline u32 pwr_falcon_irqmclr_halt_f(u32 v) | 147 | static inline u32 pwr_falcon_irqmclr_halt_f(u32 v) |
148 | { | 148 | { |
149 | return (v & 0x1) << 4; | 149 | return (v & 0x1U) << 4U; |
150 | } | 150 | } |
151 | static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v) | 151 | static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v) |
152 | { | 152 | { |
153 | return (v & 0x1) << 5; | 153 | return (v & 0x1U) << 5U; |
154 | } | 154 | } |
155 | static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v) | 155 | static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v) |
156 | { | 156 | { |
157 | return (v & 0x1) << 6; | 157 | return (v & 0x1U) << 6U; |
158 | } | 158 | } |
159 | static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v) | 159 | static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v) |
160 | { | 160 | { |
161 | return (v & 0x1) << 7; | 161 | return (v & 0x1U) << 7U; |
162 | } | 162 | } |
163 | static inline u32 pwr_falcon_irqmclr_ext_f(u32 v) | 163 | static inline u32 pwr_falcon_irqmclr_ext_f(u32 v) |
164 | { | 164 | { |
165 | return (v & 0xff) << 8; | 165 | return (v & 0xffU) << 8U; |
166 | } | 166 | } |
167 | static inline u32 pwr_falcon_irqmask_r(void) | 167 | static inline u32 pwr_falcon_irqmask_r(void) |
168 | { | 168 | { |
169 | return 0x0010a018; | 169 | return 0x0010a018U; |
170 | } | 170 | } |
171 | static inline u32 pwr_falcon_irqdest_r(void) | 171 | static inline u32 pwr_falcon_irqdest_r(void) |
172 | { | 172 | { |
173 | return 0x0010a01c; | 173 | return 0x0010a01cU; |
174 | } | 174 | } |
175 | static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v) | 175 | static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v) |
176 | { | 176 | { |
177 | return (v & 0x1) << 0; | 177 | return (v & 0x1U) << 0U; |
178 | } | 178 | } |
179 | static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v) | 179 | static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v) |
180 | { | 180 | { |
181 | return (v & 0x1) << 1; | 181 | return (v & 0x1U) << 1U; |
182 | } | 182 | } |
183 | static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v) | 183 | static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v) |
184 | { | 184 | { |
185 | return (v & 0x1) << 2; | 185 | return (v & 0x1U) << 2U; |
186 | } | 186 | } |
187 | static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v) | 187 | static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v) |
188 | { | 188 | { |
189 | return (v & 0x1) << 3; | 189 | return (v & 0x1U) << 3U; |
190 | } | 190 | } |
191 | static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v) | 191 | static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v) |
192 | { | 192 | { |
193 | return (v & 0x1) << 4; | 193 | return (v & 0x1U) << 4U; |
194 | } | 194 | } |
195 | static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v) | 195 | static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v) |
196 | { | 196 | { |
197 | return (v & 0x1) << 5; | 197 | return (v & 0x1U) << 5U; |
198 | } | 198 | } |
199 | static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v) | 199 | static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v) |
200 | { | 200 | { |
201 | return (v & 0x1) << 6; | 201 | return (v & 0x1U) << 6U; |
202 | } | 202 | } |
203 | static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v) | 203 | static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v) |
204 | { | 204 | { |
205 | return (v & 0x1) << 7; | 205 | return (v & 0x1U) << 7U; |
206 | } | 206 | } |
207 | static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v) | 207 | static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v) |
208 | { | 208 | { |
209 | return (v & 0xff) << 8; | 209 | return (v & 0xffU) << 8U; |
210 | } | 210 | } |
211 | static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v) | 211 | static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v) |
212 | { | 212 | { |
213 | return (v & 0x1) << 16; | 213 | return (v & 0x1U) << 16U; |
214 | } | 214 | } |
215 | static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v) | 215 | static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v) |
216 | { | 216 | { |
217 | return (v & 0x1) << 17; | 217 | return (v & 0x1U) << 17U; |
218 | } | 218 | } |
219 | static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v) | 219 | static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v) |
220 | { | 220 | { |
221 | return (v & 0x1) << 18; | 221 | return (v & 0x1U) << 18U; |
222 | } | 222 | } |
223 | static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v) | 223 | static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v) |
224 | { | 224 | { |
225 | return (v & 0x1) << 19; | 225 | return (v & 0x1U) << 19U; |
226 | } | 226 | } |
227 | static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v) | 227 | static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v) |
228 | { | 228 | { |
229 | return (v & 0x1) << 20; | 229 | return (v & 0x1U) << 20U; |
230 | } | 230 | } |
231 | static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v) | 231 | static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v) |
232 | { | 232 | { |
233 | return (v & 0x1) << 21; | 233 | return (v & 0x1U) << 21U; |
234 | } | 234 | } |
235 | static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v) | 235 | static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v) |
236 | { | 236 | { |
237 | return (v & 0x1) << 22; | 237 | return (v & 0x1U) << 22U; |
238 | } | 238 | } |
239 | static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v) | 239 | static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v) |
240 | { | 240 | { |
241 | return (v & 0x1) << 23; | 241 | return (v & 0x1U) << 23U; |
242 | } | 242 | } |
243 | static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v) | 243 | static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v) |
244 | { | 244 | { |
245 | return (v & 0xff) << 24; | 245 | return (v & 0xffU) << 24U; |
246 | } | 246 | } |
247 | static inline u32 pwr_falcon_curctx_r(void) | 247 | static inline u32 pwr_falcon_curctx_r(void) |
248 | { | 248 | { |
249 | return 0x0010a050; | 249 | return 0x0010a050U; |
250 | } | 250 | } |
251 | static inline u32 pwr_falcon_nxtctx_r(void) | 251 | static inline u32 pwr_falcon_nxtctx_r(void) |
252 | { | 252 | { |
253 | return 0x0010a054; | 253 | return 0x0010a054U; |
254 | } | 254 | } |
255 | static inline u32 pwr_falcon_mailbox0_r(void) | 255 | static inline u32 pwr_falcon_mailbox0_r(void) |
256 | { | 256 | { |
257 | return 0x0010a040; | 257 | return 0x0010a040U; |
258 | } | 258 | } |
259 | static inline u32 pwr_falcon_mailbox1_r(void) | 259 | static inline u32 pwr_falcon_mailbox1_r(void) |
260 | { | 260 | { |
261 | return 0x0010a044; | 261 | return 0x0010a044U; |
262 | } | 262 | } |
263 | static inline u32 pwr_falcon_itfen_r(void) | 263 | static inline u32 pwr_falcon_itfen_r(void) |
264 | { | 264 | { |
265 | return 0x0010a048; | 265 | return 0x0010a048U; |
266 | } | 266 | } |
267 | static inline u32 pwr_falcon_itfen_ctxen_enable_f(void) | 267 | static inline u32 pwr_falcon_itfen_ctxen_enable_f(void) |
268 | { | 268 | { |
269 | return 0x1; | 269 | return 0x1U; |
270 | } | 270 | } |
271 | static inline u32 pwr_falcon_idlestate_r(void) | 271 | static inline u32 pwr_falcon_idlestate_r(void) |
272 | { | 272 | { |
273 | return 0x0010a04c; | 273 | return 0x0010a04cU; |
274 | } | 274 | } |
275 | static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r) | 275 | static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r) |
276 | { | 276 | { |
277 | return (r >> 0) & 0x1; | 277 | return (r >> 0U) & 0x1U; |
278 | } | 278 | } |
279 | static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r) | 279 | static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r) |
280 | { | 280 | { |
281 | return (r >> 1) & 0x7fff; | 281 | return (r >> 1U) & 0x7fffU; |
282 | } | 282 | } |
283 | static inline u32 pwr_falcon_os_r(void) | 283 | static inline u32 pwr_falcon_os_r(void) |
284 | { | 284 | { |
285 | return 0x0010a080; | 285 | return 0x0010a080U; |
286 | } | 286 | } |
287 | static inline u32 pwr_falcon_engctl_r(void) | 287 | static inline u32 pwr_falcon_engctl_r(void) |
288 | { | 288 | { |
289 | return 0x0010a0a4; | 289 | return 0x0010a0a4U; |
290 | } | 290 | } |
291 | static inline u32 pwr_falcon_cpuctl_r(void) | 291 | static inline u32 pwr_falcon_cpuctl_r(void) |
292 | { | 292 | { |
293 | return 0x0010a100; | 293 | return 0x0010a100U; |
294 | } | 294 | } |
295 | static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v) | 295 | static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v) |
296 | { | 296 | { |
297 | return (v & 0x1) << 1; | 297 | return (v & 0x1U) << 1U; |
298 | } | 298 | } |
299 | static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v) | 299 | static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v) |
300 | { | 300 | { |
301 | return (v & 0x1) << 4; | 301 | return (v & 0x1U) << 4U; |
302 | } | 302 | } |
303 | static inline u32 pwr_falcon_cpuctl_halt_intr_m(void) | 303 | static inline u32 pwr_falcon_cpuctl_halt_intr_m(void) |
304 | { | 304 | { |
305 | return 0x1 << 4; | 305 | return 0x1U << 4U; |
306 | } | 306 | } |
307 | static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r) | 307 | static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r) |
308 | { | 308 | { |
309 | return (r >> 4) & 0x1; | 309 | return (r >> 4U) & 0x1U; |
310 | } | 310 | } |
311 | static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v) | 311 | static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v) |
312 | { | 312 | { |
313 | return (v & 0x1) << 6; | 313 | return (v & 0x1U) << 6U; |
314 | } | 314 | } |
315 | static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void) | 315 | static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void) |
316 | { | 316 | { |
317 | return 0x1 << 6; | 317 | return 0x1U << 6U; |
318 | } | 318 | } |
319 | static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r) | 319 | static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r) |
320 | { | 320 | { |
321 | return (r >> 6) & 0x1; | 321 | return (r >> 6U) & 0x1U; |
322 | } | 322 | } |
323 | static inline u32 pwr_falcon_cpuctl_alias_r(void) | 323 | static inline u32 pwr_falcon_cpuctl_alias_r(void) |
324 | { | 324 | { |
325 | return 0x0010a130; | 325 | return 0x0010a130U; |
326 | } | 326 | } |
327 | static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v) | 327 | static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v) |
328 | { | 328 | { |
329 | return (v & 0x1) << 1; | 329 | return (v & 0x1U) << 1U; |
330 | } | 330 | } |
331 | static inline u32 pwr_pmu_scpctl_stat_r(void) | 331 | static inline u32 pwr_pmu_scpctl_stat_r(void) |
332 | { | 332 | { |
333 | return 0x0010ac08; | 333 | return 0x0010ac08U; |
334 | } | 334 | } |
335 | static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v) | 335 | static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v) |
336 | { | 336 | { |
337 | return (v & 0x1) << 20; | 337 | return (v & 0x1U) << 20U; |
338 | } | 338 | } |
339 | static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void) | 339 | static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void) |
340 | { | 340 | { |
341 | return 0x1 << 20; | 341 | return 0x1U << 20U; |
342 | } | 342 | } |
343 | static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r) | 343 | static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r) |
344 | { | 344 | { |
345 | return (r >> 20) & 0x1; | 345 | return (r >> 20U) & 0x1U; |
346 | } | 346 | } |
347 | static inline u32 pwr_falcon_imemc_r(u32 i) | 347 | static inline u32 pwr_falcon_imemc_r(u32 i) |
348 | { | 348 | { |
349 | return 0x0010a180 + i*16; | 349 | return 0x0010a180U + i*16U; |
350 | } | 350 | } |
351 | static inline u32 pwr_falcon_imemc_offs_f(u32 v) | 351 | static inline u32 pwr_falcon_imemc_offs_f(u32 v) |
352 | { | 352 | { |
353 | return (v & 0x3f) << 2; | 353 | return (v & 0x3fU) << 2U; |
354 | } | 354 | } |
355 | static inline u32 pwr_falcon_imemc_blk_f(u32 v) | 355 | static inline u32 pwr_falcon_imemc_blk_f(u32 v) |
356 | { | 356 | { |
357 | return (v & 0xff) << 8; | 357 | return (v & 0xffU) << 8U; |
358 | } | 358 | } |
359 | static inline u32 pwr_falcon_imemc_aincw_f(u32 v) | 359 | static inline u32 pwr_falcon_imemc_aincw_f(u32 v) |
360 | { | 360 | { |
361 | return (v & 0x1) << 24; | 361 | return (v & 0x1U) << 24U; |
362 | } | 362 | } |
363 | static inline u32 pwr_falcon_imemd_r(u32 i) | 363 | static inline u32 pwr_falcon_imemd_r(u32 i) |
364 | { | 364 | { |
365 | return 0x0010a184 + i*16; | 365 | return 0x0010a184U + i*16U; |
366 | } | 366 | } |
367 | static inline u32 pwr_falcon_imemt_r(u32 i) | 367 | static inline u32 pwr_falcon_imemt_r(u32 i) |
368 | { | 368 | { |
369 | return 0x0010a188 + i*16; | 369 | return 0x0010a188U + i*16U; |
370 | } | 370 | } |
371 | static inline u32 pwr_falcon_sctl_r(void) | 371 | static inline u32 pwr_falcon_sctl_r(void) |
372 | { | 372 | { |
373 | return 0x0010a240; | 373 | return 0x0010a240U; |
374 | } | 374 | } |
375 | static inline u32 pwr_falcon_mmu_phys_sec_r(void) | 375 | static inline u32 pwr_falcon_mmu_phys_sec_r(void) |
376 | { | 376 | { |
377 | return 0x00100ce4; | 377 | return 0x00100ce4U; |
378 | } | 378 | } |
379 | static inline u32 pwr_falcon_bootvec_r(void) | 379 | static inline u32 pwr_falcon_bootvec_r(void) |
380 | { | 380 | { |
381 | return 0x0010a104; | 381 | return 0x0010a104U; |
382 | } | 382 | } |
383 | static inline u32 pwr_falcon_bootvec_vec_f(u32 v) | 383 | static inline u32 pwr_falcon_bootvec_vec_f(u32 v) |
384 | { | 384 | { |
385 | return (v & 0xffffffff) << 0; | 385 | return (v & 0xffffffffU) << 0U; |
386 | } | 386 | } |
387 | static inline u32 pwr_falcon_dmactl_r(void) | 387 | static inline u32 pwr_falcon_dmactl_r(void) |
388 | { | 388 | { |
389 | return 0x0010a10c; | 389 | return 0x0010a10cU; |
390 | } | 390 | } |
391 | static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void) | 391 | static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void) |
392 | { | 392 | { |
393 | return 0x1 << 1; | 393 | return 0x1U << 1U; |
394 | } | 394 | } |
395 | static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void) | 395 | static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void) |
396 | { | 396 | { |
397 | return 0x1 << 2; | 397 | return 0x1U << 2U; |
398 | } | 398 | } |
399 | static inline u32 pwr_falcon_hwcfg_r(void) | 399 | static inline u32 pwr_falcon_hwcfg_r(void) |
400 | { | 400 | { |
401 | return 0x0010a108; | 401 | return 0x0010a108U; |
402 | } | 402 | } |
403 | static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r) | 403 | static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r) |
404 | { | 404 | { |
405 | return (r >> 0) & 0x1ff; | 405 | return (r >> 0U) & 0x1ffU; |
406 | } | 406 | } |
407 | static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r) | 407 | static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r) |
408 | { | 408 | { |
409 | return (r >> 9) & 0x1ff; | 409 | return (r >> 9U) & 0x1ffU; |
410 | } | 410 | } |
411 | static inline u32 pwr_falcon_dmatrfbase_r(void) | 411 | static inline u32 pwr_falcon_dmatrfbase_r(void) |
412 | { | 412 | { |
413 | return 0x0010a110; | 413 | return 0x0010a110U; |
414 | } | 414 | } |
415 | static inline u32 pwr_falcon_dmatrfbase1_r(void) | 415 | static inline u32 pwr_falcon_dmatrfbase1_r(void) |
416 | { | 416 | { |
417 | return 0x0010a128; | 417 | return 0x0010a128U; |
418 | } | 418 | } |
419 | static inline u32 pwr_falcon_dmatrfmoffs_r(void) | 419 | static inline u32 pwr_falcon_dmatrfmoffs_r(void) |
420 | { | 420 | { |
421 | return 0x0010a114; | 421 | return 0x0010a114U; |
422 | } | 422 | } |
423 | static inline u32 pwr_falcon_dmatrfcmd_r(void) | 423 | static inline u32 pwr_falcon_dmatrfcmd_r(void) |
424 | { | 424 | { |
425 | return 0x0010a118; | 425 | return 0x0010a118U; |
426 | } | 426 | } |
427 | static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v) | 427 | static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v) |
428 | { | 428 | { |
429 | return (v & 0x1) << 4; | 429 | return (v & 0x1U) << 4U; |
430 | } | 430 | } |
431 | static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v) | 431 | static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v) |
432 | { | 432 | { |
433 | return (v & 0x1) << 5; | 433 | return (v & 0x1U) << 5U; |
434 | } | 434 | } |
435 | static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v) | 435 | static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v) |
436 | { | 436 | { |
437 | return (v & 0x7) << 8; | 437 | return (v & 0x7U) << 8U; |
438 | } | 438 | } |
439 | static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v) | 439 | static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v) |
440 | { | 440 | { |
441 | return (v & 0x7) << 12; | 441 | return (v & 0x7U) << 12U; |
442 | } | 442 | } |
443 | static inline u32 pwr_falcon_dmatrffboffs_r(void) | 443 | static inline u32 pwr_falcon_dmatrffboffs_r(void) |
444 | { | 444 | { |
445 | return 0x0010a11c; | 445 | return 0x0010a11cU; |
446 | } | 446 | } |
447 | static inline u32 pwr_falcon_exterraddr_r(void) | 447 | static inline u32 pwr_falcon_exterraddr_r(void) |
448 | { | 448 | { |
449 | return 0x0010a168; | 449 | return 0x0010a168U; |
450 | } | 450 | } |
451 | static inline u32 pwr_falcon_exterrstat_r(void) | 451 | static inline u32 pwr_falcon_exterrstat_r(void) |
452 | { | 452 | { |
453 | return 0x0010a16c; | 453 | return 0x0010a16cU; |
454 | } | 454 | } |
455 | static inline u32 pwr_falcon_exterrstat_valid_m(void) | 455 | static inline u32 pwr_falcon_exterrstat_valid_m(void) |
456 | { | 456 | { |
457 | return 0x1 << 31; | 457 | return 0x1U << 31U; |
458 | } | 458 | } |
459 | static inline u32 pwr_falcon_exterrstat_valid_v(u32 r) | 459 | static inline u32 pwr_falcon_exterrstat_valid_v(u32 r) |
460 | { | 460 | { |
461 | return (r >> 31) & 0x1; | 461 | return (r >> 31U) & 0x1U; |
462 | } | 462 | } |
463 | static inline u32 pwr_falcon_exterrstat_valid_true_v(void) | 463 | static inline u32 pwr_falcon_exterrstat_valid_true_v(void) |
464 | { | 464 | { |
465 | return 0x00000001; | 465 | return 0x00000001U; |
466 | } | 466 | } |
467 | static inline u32 pwr_pmu_falcon_icd_cmd_r(void) | 467 | static inline u32 pwr_pmu_falcon_icd_cmd_r(void) |
468 | { | 468 | { |
469 | return 0x0010a200; | 469 | return 0x0010a200U; |
470 | } | 470 | } |
471 | static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void) | 471 | static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void) |
472 | { | 472 | { |
473 | return 4; | 473 | return 4U; |
474 | } | 474 | } |
475 | static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v) | 475 | static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v) |
476 | { | 476 | { |
477 | return (v & 0xf) << 0; | 477 | return (v & 0xfU) << 0U; |
478 | } | 478 | } |
479 | static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void) | 479 | static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void) |
480 | { | 480 | { |
481 | return 0xf << 0; | 481 | return 0xfU << 0U; |
482 | } | 482 | } |
483 | static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r) | 483 | static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r) |
484 | { | 484 | { |
485 | return (r >> 0) & 0xf; | 485 | return (r >> 0U) & 0xfU; |
486 | } | 486 | } |
487 | static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void) | 487 | static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void) |
488 | { | 488 | { |
489 | return 0x8; | 489 | return 0x8U; |
490 | } | 490 | } |
491 | static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void) | 491 | static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void) |
492 | { | 492 | { |
493 | return 0xe; | 493 | return 0xeU; |
494 | } | 494 | } |
495 | static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v) | 495 | static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v) |
496 | { | 496 | { |
497 | return (v & 0x1f) << 8; | 497 | return (v & 0x1fU) << 8U; |
498 | } | 498 | } |
499 | static inline u32 pwr_pmu_falcon_icd_rdata_r(void) | 499 | static inline u32 pwr_pmu_falcon_icd_rdata_r(void) |
500 | { | 500 | { |
501 | return 0x0010a20c; | 501 | return 0x0010a20cU; |
502 | } | 502 | } |
503 | static inline u32 pwr_falcon_dmemc_r(u32 i) | 503 | static inline u32 pwr_falcon_dmemc_r(u32 i) |
504 | { | 504 | { |
505 | return 0x0010a1c0 + i*8; | 505 | return 0x0010a1c0U + i*8U; |
506 | } | 506 | } |
507 | static inline u32 pwr_falcon_dmemc_offs_f(u32 v) | 507 | static inline u32 pwr_falcon_dmemc_offs_f(u32 v) |
508 | { | 508 | { |
509 | return (v & 0x3f) << 2; | 509 | return (v & 0x3fU) << 2U; |
510 | } | 510 | } |
511 | static inline u32 pwr_falcon_dmemc_offs_m(void) | 511 | static inline u32 pwr_falcon_dmemc_offs_m(void) |
512 | { | 512 | { |
513 | return 0x3f << 2; | 513 | return 0x3fU << 2U; |
514 | } | 514 | } |
515 | static inline u32 pwr_falcon_dmemc_blk_f(u32 v) | 515 | static inline u32 pwr_falcon_dmemc_blk_f(u32 v) |
516 | { | 516 | { |
517 | return (v & 0xff) << 8; | 517 | return (v & 0xffU) << 8U; |
518 | } | 518 | } |
519 | static inline u32 pwr_falcon_dmemc_blk_m(void) | 519 | static inline u32 pwr_falcon_dmemc_blk_m(void) |
520 | { | 520 | { |
521 | return 0xff << 8; | 521 | return 0xffU << 8U; |
522 | } | 522 | } |
523 | static inline u32 pwr_falcon_dmemc_aincw_f(u32 v) | 523 | static inline u32 pwr_falcon_dmemc_aincw_f(u32 v) |
524 | { | 524 | { |
525 | return (v & 0x1) << 24; | 525 | return (v & 0x1U) << 24U; |
526 | } | 526 | } |
527 | static inline u32 pwr_falcon_dmemc_aincr_f(u32 v) | 527 | static inline u32 pwr_falcon_dmemc_aincr_f(u32 v) |
528 | { | 528 | { |
529 | return (v & 0x1) << 25; | 529 | return (v & 0x1U) << 25U; |
530 | } | 530 | } |
531 | static inline u32 pwr_falcon_dmemd_r(u32 i) | 531 | static inline u32 pwr_falcon_dmemd_r(u32 i) |
532 | { | 532 | { |
533 | return 0x0010a1c4 + i*8; | 533 | return 0x0010a1c4U + i*8U; |
534 | } | 534 | } |
535 | static inline u32 pwr_pmu_new_instblk_r(void) | 535 | static inline u32 pwr_pmu_new_instblk_r(void) |
536 | { | 536 | { |
537 | return 0x0010a480; | 537 | return 0x0010a480U; |
538 | } | 538 | } |
539 | static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v) | 539 | static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v) |
540 | { | 540 | { |
541 | return (v & 0xfffffff) << 0; | 541 | return (v & 0xfffffffU) << 0U; |
542 | } | 542 | } |
543 | static inline u32 pwr_pmu_new_instblk_target_fb_f(void) | 543 | static inline u32 pwr_pmu_new_instblk_target_fb_f(void) |
544 | { | 544 | { |
545 | return 0x0; | 545 | return 0x0U; |
546 | } | 546 | } |
547 | static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void) | 547 | static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void) |
548 | { | 548 | { |
549 | return 0x20000000; | 549 | return 0x20000000U; |
550 | } | 550 | } |
551 | static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void) | 551 | static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void) |
552 | { | 552 | { |
553 | return 0x30000000; | 553 | return 0x30000000U; |
554 | } | 554 | } |
555 | static inline u32 pwr_pmu_new_instblk_valid_f(u32 v) | 555 | static inline u32 pwr_pmu_new_instblk_valid_f(u32 v) |
556 | { | 556 | { |
557 | return (v & 0x1) << 30; | 557 | return (v & 0x1U) << 30U; |
558 | } | 558 | } |
559 | static inline u32 pwr_pmu_mutex_id_r(void) | 559 | static inline u32 pwr_pmu_mutex_id_r(void) |
560 | { | 560 | { |
561 | return 0x0010a488; | 561 | return 0x0010a488U; |
562 | } | 562 | } |
563 | static inline u32 pwr_pmu_mutex_id_value_v(u32 r) | 563 | static inline u32 pwr_pmu_mutex_id_value_v(u32 r) |
564 | { | 564 | { |
565 | return (r >> 0) & 0xff; | 565 | return (r >> 0U) & 0xffU; |
566 | } | 566 | } |
567 | static inline u32 pwr_pmu_mutex_id_value_init_v(void) | 567 | static inline u32 pwr_pmu_mutex_id_value_init_v(void) |
568 | { | 568 | { |
569 | return 0x00000000; | 569 | return 0x00000000U; |
570 | } | 570 | } |
571 | static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void) | 571 | static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void) |
572 | { | 572 | { |
573 | return 0x000000ff; | 573 | return 0x000000ffU; |
574 | } | 574 | } |
575 | static inline u32 pwr_pmu_mutex_id_release_r(void) | 575 | static inline u32 pwr_pmu_mutex_id_release_r(void) |
576 | { | 576 | { |
577 | return 0x0010a48c; | 577 | return 0x0010a48cU; |
578 | } | 578 | } |
579 | static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v) | 579 | static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v) |
580 | { | 580 | { |
581 | return (v & 0xff) << 0; | 581 | return (v & 0xffU) << 0U; |
582 | } | 582 | } |
583 | static inline u32 pwr_pmu_mutex_id_release_value_m(void) | 583 | static inline u32 pwr_pmu_mutex_id_release_value_m(void) |
584 | { | 584 | { |
585 | return 0xff << 0; | 585 | return 0xffU << 0U; |
586 | } | 586 | } |
587 | static inline u32 pwr_pmu_mutex_id_release_value_init_v(void) | 587 | static inline u32 pwr_pmu_mutex_id_release_value_init_v(void) |
588 | { | 588 | { |
589 | return 0x00000000; | 589 | return 0x00000000U; |
590 | } | 590 | } |
591 | static inline u32 pwr_pmu_mutex_id_release_value_init_f(void) | 591 | static inline u32 pwr_pmu_mutex_id_release_value_init_f(void) |
592 | { | 592 | { |
593 | return 0x0; | 593 | return 0x0U; |
594 | } | 594 | } |
595 | static inline u32 pwr_pmu_mutex_r(u32 i) | 595 | static inline u32 pwr_pmu_mutex_r(u32 i) |
596 | { | 596 | { |
597 | return 0x0010a580 + i*4; | 597 | return 0x0010a580U + i*4U; |
598 | } | 598 | } |
599 | static inline u32 pwr_pmu_mutex__size_1_v(void) | 599 | static inline u32 pwr_pmu_mutex__size_1_v(void) |
600 | { | 600 | { |
601 | return 0x00000010; | 601 | return 0x00000010U; |
602 | } | 602 | } |
603 | static inline u32 pwr_pmu_mutex_value_f(u32 v) | 603 | static inline u32 pwr_pmu_mutex_value_f(u32 v) |
604 | { | 604 | { |
605 | return (v & 0xff) << 0; | 605 | return (v & 0xffU) << 0U; |
606 | } | 606 | } |
607 | static inline u32 pwr_pmu_mutex_value_v(u32 r) | 607 | static inline u32 pwr_pmu_mutex_value_v(u32 r) |
608 | { | 608 | { |
609 | return (r >> 0) & 0xff; | 609 | return (r >> 0U) & 0xffU; |
610 | } | 610 | } |
611 | static inline u32 pwr_pmu_mutex_value_initial_lock_f(void) | 611 | static inline u32 pwr_pmu_mutex_value_initial_lock_f(void) |
612 | { | 612 | { |
613 | return 0x0; | 613 | return 0x0U; |
614 | } | 614 | } |
615 | static inline u32 pwr_pmu_queue_head_r(u32 i) | 615 | static inline u32 pwr_pmu_queue_head_r(u32 i) |
616 | { | 616 | { |
617 | return 0x0010a4a0 + i*4; | 617 | return 0x0010a4a0U + i*4U; |
618 | } | 618 | } |
619 | static inline u32 pwr_pmu_queue_head__size_1_v(void) | 619 | static inline u32 pwr_pmu_queue_head__size_1_v(void) |
620 | { | 620 | { |
621 | return 0x00000004; | 621 | return 0x00000004U; |
622 | } | 622 | } |
623 | static inline u32 pwr_pmu_queue_head_address_f(u32 v) | 623 | static inline u32 pwr_pmu_queue_head_address_f(u32 v) |
624 | { | 624 | { |
625 | return (v & 0xffffffff) << 0; | 625 | return (v & 0xffffffffU) << 0U; |
626 | } | 626 | } |
627 | static inline u32 pwr_pmu_queue_head_address_v(u32 r) | 627 | static inline u32 pwr_pmu_queue_head_address_v(u32 r) |
628 | { | 628 | { |
629 | return (r >> 0) & 0xffffffff; | 629 | return (r >> 0U) & 0xffffffffU; |
630 | } | 630 | } |
631 | static inline u32 pwr_pmu_queue_tail_r(u32 i) | 631 | static inline u32 pwr_pmu_queue_tail_r(u32 i) |
632 | { | 632 | { |
633 | return 0x0010a4b0 + i*4; | 633 | return 0x0010a4b0U + i*4U; |
634 | } | 634 | } |
635 | static inline u32 pwr_pmu_queue_tail__size_1_v(void) | 635 | static inline u32 pwr_pmu_queue_tail__size_1_v(void) |
636 | { | 636 | { |
637 | return 0x00000004; | 637 | return 0x00000004U; |
638 | } | 638 | } |
639 | static inline u32 pwr_pmu_queue_tail_address_f(u32 v) | 639 | static inline u32 pwr_pmu_queue_tail_address_f(u32 v) |
640 | { | 640 | { |
641 | return (v & 0xffffffff) << 0; | 641 | return (v & 0xffffffffU) << 0U; |
642 | } | 642 | } |
643 | static inline u32 pwr_pmu_queue_tail_address_v(u32 r) | 643 | static inline u32 pwr_pmu_queue_tail_address_v(u32 r) |
644 | { | 644 | { |
645 | return (r >> 0) & 0xffffffff; | 645 | return (r >> 0U) & 0xffffffffU; |
646 | } | 646 | } |
647 | static inline u32 pwr_pmu_msgq_head_r(void) | 647 | static inline u32 pwr_pmu_msgq_head_r(void) |
648 | { | 648 | { |
649 | return 0x0010a4c8; | 649 | return 0x0010a4c8U; |
650 | } | 650 | } |
651 | static inline u32 pwr_pmu_msgq_head_val_f(u32 v) | 651 | static inline u32 pwr_pmu_msgq_head_val_f(u32 v) |
652 | { | 652 | { |
653 | return (v & 0xffffffff) << 0; | 653 | return (v & 0xffffffffU) << 0U; |
654 | } | 654 | } |
655 | static inline u32 pwr_pmu_msgq_head_val_v(u32 r) | 655 | static inline u32 pwr_pmu_msgq_head_val_v(u32 r) |
656 | { | 656 | { |
657 | return (r >> 0) & 0xffffffff; | 657 | return (r >> 0U) & 0xffffffffU; |
658 | } | 658 | } |
659 | static inline u32 pwr_pmu_msgq_tail_r(void) | 659 | static inline u32 pwr_pmu_msgq_tail_r(void) |
660 | { | 660 | { |
661 | return 0x0010a4cc; | 661 | return 0x0010a4ccU; |
662 | } | 662 | } |
663 | static inline u32 pwr_pmu_msgq_tail_val_f(u32 v) | 663 | static inline u32 pwr_pmu_msgq_tail_val_f(u32 v) |
664 | { | 664 | { |
665 | return (v & 0xffffffff) << 0; | 665 | return (v & 0xffffffffU) << 0U; |
666 | } | 666 | } |
667 | static inline u32 pwr_pmu_msgq_tail_val_v(u32 r) | 667 | static inline u32 pwr_pmu_msgq_tail_val_v(u32 r) |
668 | { | 668 | { |
669 | return (r >> 0) & 0xffffffff; | 669 | return (r >> 0U) & 0xffffffffU; |
670 | } | 670 | } |
671 | static inline u32 pwr_pmu_idle_mask_r(u32 i) | 671 | static inline u32 pwr_pmu_idle_mask_r(u32 i) |
672 | { | 672 | { |
673 | return 0x0010a504 + i*16; | 673 | return 0x0010a504U + i*16U; |
674 | } | 674 | } |
675 | static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void) | 675 | static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void) |
676 | { | 676 | { |
677 | return 0x1; | 677 | return 0x1U; |
678 | } | 678 | } |
679 | static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void) | 679 | static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void) |
680 | { | 680 | { |
681 | return 0x200000; | 681 | return 0x200000U; |
682 | } | 682 | } |
683 | static inline u32 pwr_pmu_idle_count_r(u32 i) | 683 | static inline u32 pwr_pmu_idle_count_r(u32 i) |
684 | { | 684 | { |
685 | return 0x0010a508 + i*16; | 685 | return 0x0010a508U + i*16U; |
686 | } | 686 | } |
687 | static inline u32 pwr_pmu_idle_count_value_f(u32 v) | 687 | static inline u32 pwr_pmu_idle_count_value_f(u32 v) |
688 | { | 688 | { |
689 | return (v & 0x7fffffff) << 0; | 689 | return (v & 0x7fffffffU) << 0U; |
690 | } | 690 | } |
691 | static inline u32 pwr_pmu_idle_count_value_v(u32 r) | 691 | static inline u32 pwr_pmu_idle_count_value_v(u32 r) |
692 | { | 692 | { |
693 | return (r >> 0) & 0x7fffffff; | 693 | return (r >> 0U) & 0x7fffffffU; |
694 | } | 694 | } |
695 | static inline u32 pwr_pmu_idle_count_reset_f(u32 v) | 695 | static inline u32 pwr_pmu_idle_count_reset_f(u32 v) |
696 | { | 696 | { |
697 | return (v & 0x1) << 31; | 697 | return (v & 0x1U) << 31U; |
698 | } | 698 | } |
699 | static inline u32 pwr_pmu_idle_ctrl_r(u32 i) | 699 | static inline u32 pwr_pmu_idle_ctrl_r(u32 i) |
700 | { | 700 | { |
701 | return 0x0010a50c + i*16; | 701 | return 0x0010a50cU + i*16U; |
702 | } | 702 | } |
703 | static inline u32 pwr_pmu_idle_ctrl_value_m(void) | 703 | static inline u32 pwr_pmu_idle_ctrl_value_m(void) |
704 | { | 704 | { |
705 | return 0x3 << 0; | 705 | return 0x3U << 0U; |
706 | } | 706 | } |
707 | static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void) | 707 | static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void) |
708 | { | 708 | { |
709 | return 0x2; | 709 | return 0x2U; |
710 | } | 710 | } |
711 | static inline u32 pwr_pmu_idle_ctrl_value_always_f(void) | 711 | static inline u32 pwr_pmu_idle_ctrl_value_always_f(void) |
712 | { | 712 | { |
713 | return 0x3; | 713 | return 0x3U; |
714 | } | 714 | } |
715 | static inline u32 pwr_pmu_idle_ctrl_filter_m(void) | 715 | static inline u32 pwr_pmu_idle_ctrl_filter_m(void) |
716 | { | 716 | { |
717 | return 0x1 << 2; | 717 | return 0x1U << 2U; |
718 | } | 718 | } |
719 | static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void) | 719 | static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void) |
720 | { | 720 | { |
721 | return 0x0; | 721 | return 0x0U; |
722 | } | 722 | } |
723 | static inline u32 pwr_pmu_idle_mask_supp_r(u32 i) | 723 | static inline u32 pwr_pmu_idle_mask_supp_r(u32 i) |
724 | { | 724 | { |
725 | return 0x0010a9f0 + i*8; | 725 | return 0x0010a9f0U + i*8U; |
726 | } | 726 | } |
727 | static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i) | 727 | static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i) |
728 | { | 728 | { |
729 | return 0x0010a9f4 + i*8; | 729 | return 0x0010a9f4U + i*8U; |
730 | } | 730 | } |
731 | static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i) | 731 | static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i) |
732 | { | 732 | { |
733 | return 0x0010aa30 + i*8; | 733 | return 0x0010aa30U + i*8U; |
734 | } | 734 | } |
735 | static inline u32 pwr_pmu_debug_r(u32 i) | 735 | static inline u32 pwr_pmu_debug_r(u32 i) |
736 | { | 736 | { |
737 | return 0x0010a5c0 + i*4; | 737 | return 0x0010a5c0U + i*4U; |
738 | } | 738 | } |
739 | static inline u32 pwr_pmu_debug__size_1_v(void) | 739 | static inline u32 pwr_pmu_debug__size_1_v(void) |
740 | { | 740 | { |
741 | return 0x00000004; | 741 | return 0x00000004U; |
742 | } | 742 | } |
743 | static inline u32 pwr_pmu_mailbox_r(u32 i) | 743 | static inline u32 pwr_pmu_mailbox_r(u32 i) |
744 | { | 744 | { |
745 | return 0x0010a450 + i*4; | 745 | return 0x0010a450U + i*4U; |
746 | } | 746 | } |
747 | static inline u32 pwr_pmu_mailbox__size_1_v(void) | 747 | static inline u32 pwr_pmu_mailbox__size_1_v(void) |
748 | { | 748 | { |
749 | return 0x0000000c; | 749 | return 0x0000000cU; |
750 | } | 750 | } |
751 | static inline u32 pwr_pmu_bar0_addr_r(void) | 751 | static inline u32 pwr_pmu_bar0_addr_r(void) |
752 | { | 752 | { |
753 | return 0x0010a7a0; | 753 | return 0x0010a7a0U; |
754 | } | 754 | } |
755 | static inline u32 pwr_pmu_bar0_data_r(void) | 755 | static inline u32 pwr_pmu_bar0_data_r(void) |
756 | { | 756 | { |
757 | return 0x0010a7a4; | 757 | return 0x0010a7a4U; |
758 | } | 758 | } |
759 | static inline u32 pwr_pmu_bar0_ctl_r(void) | 759 | static inline u32 pwr_pmu_bar0_ctl_r(void) |
760 | { | 760 | { |
761 | return 0x0010a7ac; | 761 | return 0x0010a7acU; |
762 | } | 762 | } |
763 | static inline u32 pwr_pmu_bar0_timeout_r(void) | 763 | static inline u32 pwr_pmu_bar0_timeout_r(void) |
764 | { | 764 | { |
765 | return 0x0010a7a8; | 765 | return 0x0010a7a8U; |
766 | } | 766 | } |
767 | static inline u32 pwr_pmu_bar0_fecs_error_r(void) | 767 | static inline u32 pwr_pmu_bar0_fecs_error_r(void) |
768 | { | 768 | { |
769 | return 0x0010a988; | 769 | return 0x0010a988U; |
770 | } | 770 | } |
771 | static inline u32 pwr_pmu_bar0_error_status_r(void) | 771 | static inline u32 pwr_pmu_bar0_error_status_r(void) |
772 | { | 772 | { |
773 | return 0x0010a7b0; | 773 | return 0x0010a7b0U; |
774 | } | 774 | } |
775 | static inline u32 pwr_pmu_pg_idlefilth_r(u32 i) | 775 | static inline u32 pwr_pmu_pg_idlefilth_r(u32 i) |
776 | { | 776 | { |
777 | return 0x0010a6c0 + i*4; | 777 | return 0x0010a6c0U + i*4U; |
778 | } | 778 | } |
779 | static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i) | 779 | static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i) |
780 | { | 780 | { |
781 | return 0x0010a6e8 + i*4; | 781 | return 0x0010a6e8U + i*4U; |
782 | } | 782 | } |
783 | static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i) | 783 | static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i) |
784 | { | 784 | { |
785 | return 0x0010a710 + i*4; | 785 | return 0x0010a710U + i*4U; |
786 | } | 786 | } |
787 | static inline u32 pwr_pmu_pg_intren_r(u32 i) | 787 | static inline u32 pwr_pmu_pg_intren_r(u32 i) |
788 | { | 788 | { |
789 | return 0x0010a760 + i*4; | 789 | return 0x0010a760U + i*4U; |
790 | } | 790 | } |
791 | static inline u32 pwr_fbif_transcfg_r(u32 i) | 791 | static inline u32 pwr_fbif_transcfg_r(u32 i) |
792 | { | 792 | { |
793 | return 0x0010ae00 + i*4; | 793 | return 0x0010ae00U + i*4U; |
794 | } | 794 | } |
795 | static inline u32 pwr_fbif_transcfg_target_local_fb_f(void) | 795 | static inline u32 pwr_fbif_transcfg_target_local_fb_f(void) |
796 | { | 796 | { |
797 | return 0x0; | 797 | return 0x0U; |
798 | } | 798 | } |
799 | static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void) | 799 | static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void) |
800 | { | 800 | { |
801 | return 0x1; | 801 | return 0x1U; |
802 | } | 802 | } |
803 | static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void) | 803 | static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void) |
804 | { | 804 | { |
805 | return 0x2; | 805 | return 0x2U; |
806 | } | 806 | } |
807 | static inline u32 pwr_fbif_transcfg_mem_type_s(void) | 807 | static inline u32 pwr_fbif_transcfg_mem_type_s(void) |
808 | { | 808 | { |
809 | return 1; | 809 | return 1U; |
810 | } | 810 | } |
811 | static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v) | 811 | static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v) |
812 | { | 812 | { |
813 | return (v & 0x1) << 2; | 813 | return (v & 0x1U) << 2U; |
814 | } | 814 | } |
815 | static inline u32 pwr_fbif_transcfg_mem_type_m(void) | 815 | static inline u32 pwr_fbif_transcfg_mem_type_m(void) |
816 | { | 816 | { |
817 | return 0x1 << 2; | 817 | return 0x1U << 2U; |
818 | } | 818 | } |
819 | static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r) | 819 | static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r) |
820 | { | 820 | { |
821 | return (r >> 2) & 0x1; | 821 | return (r >> 2U) & 0x1U; |
822 | } | 822 | } |
823 | static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void) | 823 | static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void) |
824 | { | 824 | { |
825 | return 0x0; | 825 | return 0x0U; |
826 | } | 826 | } |
827 | static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void) | 827 | static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void) |
828 | { | 828 | { |
829 | return 0x4; | 829 | return 0x4U; |
830 | } | 830 | } |
831 | #endif | 831 | #endif |