gpu: nvgpu: Fix priv ring error detection

Use hardware headers instead of hardcoded register numbers in priv
ring. This required updating the priv ring headers to add all the
registers and fields needed.

Incidentally this also gets rid of a lot of GPC priv ring registers
as they're not used in our code.

Also delete duplicate prints for the same information. We were
dumping GPC error also in gk20a_pbus_isr(), and we dumped master
information twice.

Dump status of each GPC separately instead of supporting only GPC0.

Change-Id: Ic50817ecc50892618fa27947fa83b05148b2cd6a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1295481
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>

1 files changed, 73 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_gpc_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_gpc_gp10b.h
new file mode 100644
index 00000000..5194ad83
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_gpc_gp10b.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pri_ringstation_gpc_gp10b_h_
+#define _hw_pri_ringstation_gpc_gp10b_h_
+
+static inline u32 pri_ringstation_gpc_master_config_r(u32 i)
+{
+        return 0x00128300 + i*4;
+}
+static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void)
+{
+        return 0x00128120;
+}
+static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void)
+{
+        return 0x00128124;
+}
+static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void)
+{
+        return 0x00128128;
+}
+static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void)
+{
+        return 0x0012812c;
+}
+#endif