gpu: nvgpu: Sync kernel headers with generator tool

HW headers in nvgpu have gotten a bit out of date. Regenerate
headers and add the following registers:

* Add PTIMER timeout registers to all chips
* Add PD, SCC, SSYNC and MME interrupt registers to all chips
* Add HWW ESR INFO register to all chips

Change-Id: I34e09371083ac1568666b0cd487a106fad56aa12
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1807709
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2 files changed, 37 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h
index 30bce9f9..be05d031 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h
@@ -184,6 +184,22 @@ static inline u32 gr_exception_sked_m(void)
 {
         return 0x1U << 8U;
 }
+static inline u32 gr_exception_pd_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 gr_exception_scc_m(void)
+{
+        return 0x1U << 3U;
+}
+static inline u32 gr_exception_ssync_m(void)
+{
+        return 0x1U << 5U;
+}
+static inline u32 gr_exception_mme_m(void)
+{
+        return 0x1U << 7U;
+}
 static inline u32 gr_exception1_r(void)
 {
         return 0x00400118U;
@@ -544,6 +560,10 @@ static inline u32 gr_fe_hww_esr_en_enable_f(void)
 {
         return 0x80000000U;
 }
+static inline u32 gr_fe_hww_esr_info_r(void)
+{
+        return 0x004041b0U;
+}
 static inline u32 gr_fe_go_idle_timeout_r(void)
 {
         return 0x00404154U;
@@ -596,6 +616,10 @@ static inline u32 gr_mme_hww_esr_en_enable_f(void)
 {
         return 0x80000000U;
 }
+static inline u32 gr_mme_hww_esr_info_r(void)
+{
+        return 0x00404494U;
+}
 static inline u32 gr_memfmt_hww_esr_r(void)
 {
         return 0x00404600U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_timer_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_timer_gm20b.h
index 38548645..f4093679 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_timer_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_timer_gm20b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -96,6 +96,18 @@ static inline u32 timer_pri_timeout_save_0_r(void)
 {
         return 0x00009084U;
 }
+static inline u32 timer_pri_timeout_save_0_fecs_tgt_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 timer_pri_timeout_save_0_addr_v(u32 r)
+{
+        return (r >> 2U) & 0x3fffffU;
+}
+static inline u32 timer_pri_timeout_save_0_write_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
 static inline u32 timer_pri_timeout_save_1_r(void)
 {
         return 0x00009088U;