gpu: nvgpu: Sync kernel headers with generator tool

HW headers in nvgpu have gotten a bit out of date. Regenerate
headers and add the following registers:

* Add PTIMER timeout registers to all chips
* Add PD, SCC, SSYNC and MME interrupt registers to all chips
* Add HWW ESR INFO register to all chips

Change-Id: I34e09371083ac1568666b0cd487a106fad56aa12
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1807709
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 4 insertions, 4 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_timer_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_timer_gk20a.h
index f0dbfc30..972d68af 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_timer_gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_timer_gk20a.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2013-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -98,15 +98,15 @@ static inline u32 timer_pri_timeout_save_0_r(void)
 }
 static inline u32 timer_pri_timeout_save_0_fecs_tgt_v(u32 r)
 {
-        return (r >> 31) & 0x1;
+        return (r >> 31U) & 0x1U;
 }
 static inline u32 timer_pri_timeout_save_0_addr_v(u32 r)
 {
-        return (r >> 2) & 0x3fffff;
+        return (r >> 2U) & 0x3fffffU;
 }
 static inline u32 timer_pri_timeout_save_0_write_v(u32 r)
 {
-        return (r >> 1) & 0x1;
+        return (r >> 1U) & 0x1U;
 }
 static inline u32 timer_pri_timeout_save_1_r(void)
 {