diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2016-09-19 01:37:46 -0400 |
---|---|---|
committer | Deepak Nibade <dnibade@nvidia.com> | 2016-12-27 04:56:50 -0500 |
commit | 173bdefc92e2e4ef8f1e7e6ead7f86e746bee935 (patch) | |
tree | 69d9a43a453e988c54927ade2f5ce04457eaf312 /drivers/gpu/nvgpu/include/bios.h | |
parent | db529935a5f50e9e683d44d2eb01d0d76a915792 (diff) |
gpu: nvgpu: add support for voltage config
- changes to read voltage tables from VBIOS
& create boardobj then send to pmu
- Rail, Device & Policy objects are read from VBIOS & created boardobjs
- RPC support to load, Set & get voltage.
JIRA DNVGPU-122
Change-Id: I61621a514eef9c081a64c4ab066f01dfc28f8402
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1222774
(cherry picked from commit 9da86d8c2c547623cf5f38c89afeb3f5bb1667ac)
Reviewed-on: http://git-master/r/1244656
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/include/bios.h')
-rw-r--r-- | drivers/gpu/nvgpu/include/bios.h | 132 |
1 files changed, 132 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/include/bios.h b/drivers/gpu/nvgpu/include/bios.h index d3a677f8..fb1e1f46 100644 --- a/drivers/gpu/nvgpu/include/bios.h +++ b/drivers/gpu/nvgpu/include/bios.h | |||
@@ -656,4 +656,136 @@ struct pwr_policy_3x_entry_struct { | |||
656 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM1_HW_THRESHOLD_LOW_THRESHOLD_VAL_MASK 0xFFFF | 656 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM1_HW_THRESHOLD_LOW_THRESHOLD_VAL_MASK 0xFFFF |
657 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM1_HW_THRESHOLD_LOW_THRESHOLD_VAL_SHIFT 0 | 657 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM1_HW_THRESHOLD_LOW_THRESHOLD_VAL_SHIFT 0 |
658 | 658 | ||
659 | /* Voltage Rail Table */ | ||
660 | struct vbios_voltage_rail_table_1x_header { | ||
661 | u8 version; | ||
662 | u8 header_size; | ||
663 | u8 table_entry_size; | ||
664 | u8 num_table_entries; | ||
665 | u8 volt_domain_hal; | ||
666 | } __packed; | ||
667 | |||
668 | #define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_07 0X00000007 | ||
669 | #define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_08 0X00000008 | ||
670 | #define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_09 0X00000009 | ||
671 | #define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0A 0X0000000A | ||
672 | #define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0B 0X0000000B | ||
673 | |||
674 | struct vbios_voltage_rail_table_1x_entry { | ||
675 | u32 boot_voltage_uv; | ||
676 | u8 rel_limit_vfe_equ_idx; | ||
677 | u8 alt_rel_limit_vfe_equidx; | ||
678 | u8 ov_limit_vfe_equ_idx; | ||
679 | u8 pwr_equ_idx; | ||
680 | u8 boot_volt_vfe_equ_idx; | ||
681 | u8 vmin_limit_vfe_equ_idx; | ||
682 | u8 volt_margin_limit_vfe_equ_idx; | ||
683 | } __packed; | ||
684 | |||
685 | /* Voltage Device Table */ | ||
686 | struct vbios_voltage_device_table_1x_header { | ||
687 | u8 version; | ||
688 | u8 header_size; | ||
689 | u8 table_entry_size; | ||
690 | u8 num_table_entries; | ||
691 | }; | ||
692 | |||
693 | struct vbios_voltage_device_table_1x_entry { | ||
694 | u8 type; | ||
695 | u8 volt_domain; | ||
696 | u16 settle_time_us; | ||
697 | u32 param0; | ||
698 | u32 param1; | ||
699 | u32 param2; | ||
700 | u32 param3; | ||
701 | u32 param4; | ||
702 | }; | ||
703 | |||
704 | #define NV_VBIOS_VOLTAGE_DEVICE_1X_ENTRY_TYPE_INVALID 0x00 | ||
705 | #define NV_VBIOS_VOLTAGE_DEVICE_1X_ENTRY_TYPE_PSV 0x02 | ||
706 | |||
707 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_INPUT_FREQUENCY_MASK \ | ||
708 | GENMASK(23, 0) | ||
709 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_INPUT_FREQUENCY_SHIFT 0 | ||
710 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_EXT_DEVICE_INDEX_MASK \ | ||
711 | GENMASK(31, 24) | ||
712 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_EXT_DEVICE_INDEX_SHIFT 24 | ||
713 | |||
714 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_VOLTAGE_MINIMUM_MASK \ | ||
715 | GENMASK(23, 0) | ||
716 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_VOLTAGE_MINIMUM_SHIFT 0 | ||
717 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_MASK \ | ||
718 | GENMASK(31, 24) | ||
719 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_SHIFT 24 | ||
720 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_DEFAULT 0x00 | ||
721 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_LPWR_STEADY_STATE \ | ||
722 | 0x01 | ||
723 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_LPWR_SLEEP_STATE \ | ||
724 | 0x02 | ||
725 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_VOLTAGE_MAXIMUM_MASK \ | ||
726 | GENMASK(23, 0) | ||
727 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_VOLTAGE_MAXIMUM_SHIFT 0 | ||
728 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_RSVD_MASK \ | ||
729 | GENMASK(31, 24) | ||
730 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_RSVD_SHIFT 24 | ||
731 | |||
732 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_BASE_MASK \ | ||
733 | GENMASK(23, 0) | ||
734 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_BASE_SHIFT 0 | ||
735 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_STEPS_MASK \ | ||
736 | GENMASK(31, 24) | ||
737 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_STEPS_SHIFT 24 | ||
738 | |||
739 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_OFFSET_SCALE_MASK \ | ||
740 | GENMASK(23, 0) | ||
741 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_OFFSET_SCALE_SHIFT 0 | ||
742 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_RSVD_MASK \ | ||
743 | GENMASK(31, 24) | ||
744 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_RSVD_SHIFT 24 | ||
745 | |||
746 | /* Voltage Policy Table */ | ||
747 | struct vbios_voltage_policy_table_1x_header { | ||
748 | u8 version; | ||
749 | u8 header_size; | ||
750 | u8 table_entry_size; | ||
751 | u8 num_table_entries; | ||
752 | u8 perf_core_vf_seq_policy_idx; | ||
753 | }; | ||
754 | |||
755 | struct vbios_voltage_policy_table_1x_entry { | ||
756 | u8 type; | ||
757 | u32 param0; | ||
758 | u32 param1; | ||
759 | }; | ||
760 | |||
761 | #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_INVALID 0x00 | ||
762 | #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SINGLE_RAIL 0x01 | ||
763 | #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SR_MULTI_STEP 0x02 | ||
764 | #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SR_SINGLE_STEP 0x03 | ||
765 | |||
766 | #define NV_VBIOS_VPT_ENTRY_PARAM0_SINGLE_RAIL_VOLT_DOMAIN_MASK \ | ||
767 | GENMASK(7, 0) | ||
768 | #define NV_VBIOS_VPT_ENTRY_PARAM0_SINGLE_RAIL_VOLT_DOMAIN_SHIFT 0 | ||
769 | #define NV_VBIOS_VPT_ENTRY_PARAM0_RSVD_MASK GENMASK(8, 31) | ||
770 | #define NV_VBIOS_VPT_ENTRY_PARAM0_RSVD_SHIFT 8 | ||
771 | |||
772 | #define NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_MASTER_MASK \ | ||
773 | GENMASK(7, 0) | ||
774 | #define NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_MASTER_SHIFT 0 | ||
775 | #define NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_SLAVE_MASK \ | ||
776 | GENMASK(15, 8) | ||
777 | #define NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_SLAVE_SHIFT 8 | ||
778 | #define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MIN_MASK \ | ||
779 | GENMASK(23, 16) | ||
780 | #define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MIN_SHIFT 16 | ||
781 | #define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MAX_MASK \ | ||
782 | GENMASK(31, 24) | ||
783 | #define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MAX_SHIFT 24 | ||
784 | |||
785 | /* Type-Specific Parameter DWORD 0 - Type = _SR_MULTI_STEP */ | ||
786 | #define NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE_MASK \ | ||
787 | GENMASK(15, 0) | ||
788 | #define NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE_SHIFT \ | ||
789 | 0 | ||
790 | |||
659 | #endif | 791 | #endif |