diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-06-21 13:34:20 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-06-30 03:05:04 -0400 |
commit | fd80220dd30ec59f270b435dff8a0e0f512d0c98 (patch) | |
tree | 76b3a276a8e89d5b073c83a489b5b2f66d9d1ca4 /drivers/gpu/nvgpu/gv11b | |
parent | c5e68d6afa664b49a2045a826f83c46ee4c4485e (diff) |
gpu: nvgpu: gv11b: init trigger_suspend gr ops
Add gv11b specific trigger_suspend function. SM register
addresses have changed as compared to legacy gpu chips.
JIRA GPUT19X-75
Change-Id: Ic3099e53bcba19128711a88ecc9e9883f5f7a31f
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1476532
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 0158d706..58bb08a6 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -2444,6 +2444,28 @@ static void gv11b_gr_get_esr_sm_sel(struct gk20a *g, u32 gpc, u32 tpc, | |||
2444 | "esr_sm_sel bitmask: 0x%x", *esr_sm_sel); | 2444 | "esr_sm_sel bitmask: 0x%x", *esr_sm_sel); |
2445 | } | 2445 | } |
2446 | 2446 | ||
2447 | static int gv11b_gr_sm_trigger_suspend(struct gk20a *g) | ||
2448 | { | ||
2449 | u32 dbgr_control0; | ||
2450 | |||
2451 | /* assert stop trigger. uniformity assumption: all SMs will have | ||
2452 | * the same state in dbg_control0. | ||
2453 | */ | ||
2454 | dbgr_control0 = | ||
2455 | gk20a_readl(g, gr_gpcs_tpcs_sms_dbgr_control0_r()); | ||
2456 | dbgr_control0 |= gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_enable_f(); | ||
2457 | |||
2458 | /* broadcast write */ | ||
2459 | gk20a_writel(g, | ||
2460 | gr_gpcs_tpcs_sms_dbgr_control0_r(), dbgr_control0); | ||
2461 | |||
2462 | gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, | ||
2463 | "stop trigger enable: broadcast dbgr_control0: 0x%x ", | ||
2464 | dbgr_control0); | ||
2465 | |||
2466 | return 0; | ||
2467 | } | ||
2468 | |||
2447 | void gv11b_init_gr(struct gpu_ops *gops) | 2469 | void gv11b_init_gr(struct gpu_ops *gops) |
2448 | { | 2470 | { |
2449 | gp10b_init_gr(gops); | 2471 | gp10b_init_gr(gops); |
@@ -2506,4 +2528,5 @@ void gv11b_init_gr(struct gpu_ops *gops) | |||
2506 | gops->gr.handle_gpc_gpcmmu_exception = | 2528 | gops->gr.handle_gpc_gpcmmu_exception = |
2507 | gr_gv11b_handle_gpc_gpcmmu_exception; | 2529 | gr_gv11b_handle_gpc_gpcmmu_exception; |
2508 | gops->gr.get_esr_sm_sel = gv11b_gr_get_esr_sm_sel; | 2530 | gops->gr.get_esr_sm_sel = gv11b_gr_get_esr_sm_sel; |
2531 | gops->gr.trigger_suspend = gv11b_gr_sm_trigger_suspend; | ||
2509 | } | 2532 | } |