diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-06-21 13:48:23 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-06-30 03:05:04 -0400 |
commit | f2235085d136c50c63d4f66d4baa00f1b46bf22a (patch) | |
tree | 67072f568117e9a9c73df5df8474b1cb27dde81a /drivers/gpu/nvgpu/gv11b | |
parent | fd80220dd30ec59f270b435dff8a0e0f512d0c98 (diff) |
gpu: nvgpu: gv11b: init bpt_reg_info gr ops
Take care of t19x reg address changes to support multiple SM
JIRA GPUT19X-75
Change-Id: I92b97e60ac82c50a97fe44a85482437446479800
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1477694
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 69 |
1 files changed, 69 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 58bb08a6..eab78119 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -2466,6 +2466,74 @@ static int gv11b_gr_sm_trigger_suspend(struct gk20a *g) | |||
2466 | return 0; | 2466 | return 0; |
2467 | } | 2467 | } |
2468 | 2468 | ||
2469 | static void gv11b_gr_bpt_reg_info(struct gk20a *g, struct warpstate *w_state) | ||
2470 | { | ||
2471 | /* Check if we have at least one valid warp | ||
2472 | * get paused state on maxwell | ||
2473 | */ | ||
2474 | struct gr_gk20a *gr = &g->gr; | ||
2475 | u32 gpc, tpc, sm, sm_id; | ||
2476 | u32 offset; | ||
2477 | u64 warps_valid = 0, warps_paused = 0, warps_trapped = 0; | ||
2478 | |||
2479 | for (sm_id = 0; sm_id < gr->no_of_sm; sm_id++) { | ||
2480 | gpc = g->gr.sm_to_cluster[sm_id].gpc_index; | ||
2481 | tpc = g->gr.sm_to_cluster[sm_id].tpc_index; | ||
2482 | sm = g->gr.sm_to_cluster[sm_id].sm_index; | ||
2483 | |||
2484 | offset = gk20a_gr_gpc_offset(g, gpc) + | ||
2485 | gk20a_gr_tpc_offset(g, tpc) + | ||
2486 | gv11b_gr_sm_offset(g, sm); | ||
2487 | |||
2488 | /* 64 bit read */ | ||
2489 | warps_valid = (u64)gk20a_readl(g, | ||
2490 | gr_gpc0_tpc0_sm0_warp_valid_mask_r() + | ||
2491 | offset + 4) << 32; | ||
2492 | warps_valid |= gk20a_readl(g, | ||
2493 | gr_gpc0_tpc0_sm0_warp_valid_mask_r() + | ||
2494 | offset); | ||
2495 | |||
2496 | /* 64 bit read */ | ||
2497 | warps_paused = (u64)gk20a_readl(g, | ||
2498 | gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_r() + | ||
2499 | offset + 4) << 32; | ||
2500 | warps_paused |= gk20a_readl(g, | ||
2501 | gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_r() + | ||
2502 | offset); | ||
2503 | |||
2504 | /* 64 bit read */ | ||
2505 | warps_trapped = (u64)gk20a_readl(g, | ||
2506 | gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_r() + | ||
2507 | offset + 4) << 32; | ||
2508 | warps_trapped |= gk20a_readl(g, | ||
2509 | gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_r() + | ||
2510 | offset); | ||
2511 | |||
2512 | w_state[sm_id].valid_warps[0] = warps_valid; | ||
2513 | w_state[sm_id].trapped_warps[0] = warps_trapped; | ||
2514 | w_state[sm_id].paused_warps[0] = warps_paused; | ||
2515 | } | ||
2516 | |||
2517 | |||
2518 | /* Only for debug purpose */ | ||
2519 | for (sm_id = 0; sm_id < gr->no_of_sm; sm_id++) { | ||
2520 | gk20a_dbg_fn("w_state[%d].valid_warps[0]: %llx\n", | ||
2521 | sm_id, w_state[sm_id].valid_warps[0]); | ||
2522 | gk20a_dbg_fn("w_state[%d].valid_warps[1]: %llx\n", | ||
2523 | sm_id, w_state[sm_id].valid_warps[1]); | ||
2524 | |||
2525 | gk20a_dbg_fn("w_state[%d].trapped_warps[0]: %llx\n", | ||
2526 | sm_id, w_state[sm_id].trapped_warps[0]); | ||
2527 | gk20a_dbg_fn("w_state[%d].trapped_warps[1]: %llx\n", | ||
2528 | sm_id, w_state[sm_id].trapped_warps[1]); | ||
2529 | |||
2530 | gk20a_dbg_fn("w_state[%d].paused_warps[0]: %llx\n", | ||
2531 | sm_id, w_state[sm_id].paused_warps[0]); | ||
2532 | gk20a_dbg_fn("w_state[%d].paused_warps[1]: %llx\n", | ||
2533 | sm_id, w_state[sm_id].paused_warps[1]); | ||
2534 | } | ||
2535 | } | ||
2536 | |||
2469 | void gv11b_init_gr(struct gpu_ops *gops) | 2537 | void gv11b_init_gr(struct gpu_ops *gops) |
2470 | { | 2538 | { |
2471 | gp10b_init_gr(gops); | 2539 | gp10b_init_gr(gops); |
@@ -2529,4 +2597,5 @@ void gv11b_init_gr(struct gpu_ops *gops) | |||
2529 | gr_gv11b_handle_gpc_gpcmmu_exception; | 2597 | gr_gv11b_handle_gpc_gpcmmu_exception; |
2530 | gops->gr.get_esr_sm_sel = gv11b_gr_get_esr_sm_sel; | 2598 | gops->gr.get_esr_sm_sel = gv11b_gr_get_esr_sm_sel; |
2531 | gops->gr.trigger_suspend = gv11b_gr_sm_trigger_suspend; | 2599 | gops->gr.trigger_suspend = gv11b_gr_sm_trigger_suspend; |
2600 | gops->gr.bpt_reg_info = gv11b_gr_bpt_reg_info; | ||
2532 | } | 2601 | } |