diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2018-01-16 06:07:37 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-02-07 18:35:47 -0500 |
commit | f0cbe19b12524f5df6466eaf86acbfb349def6b1 (patch) | |
tree | bed8a312e29592d41d9de4afb331756c2d38fb96 /drivers/gpu/nvgpu/gv11b | |
parent | 0c8deb74aff6d0781cdf3278f56d7bce42b16a67 (diff) |
gpu: nvgpu: add user API to get read-only syncpoint address map
Add User space API NVGPU_AS_IOCTL_GET_SYNC_RO_MAP to get read-only syncpoint
address map in user space
We already map whole syncpoint shim to each address space with base address
being vm->syncpt_ro_map_gpu_va
This new API exposes this base GPU_VA address of syncpoint map, and unit size
of each syncpoint to user space.
User space can then calculate address of each syncpoint as
syncpoint_address = base_gpu_va + (syncpoint_id * syncpoint_unit_size)
Note that this syncpoint address is read_only, and should be only used for
inserting semaphore acquires.
Adding semaphore release with this address would result in MMU_FAULT
Define new HAL g->ops.fifo.get_sync_ro_map and set this for all GPUs supported
on Xavier SoC
Bug 200327559
Change-Id: Ica0db48fc28fdd0ff2a5eb09574dac843dc5e4fd
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1649365
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 56 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 |
3 files changed, 47 insertions, 14 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 271dcc41..41d14a82 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | |||
@@ -1657,31 +1657,43 @@ void gv11b_fifo_deinit_eng_method_buffers(struct gk20a *g, | |||
1657 | } | 1657 | } |
1658 | 1658 | ||
1659 | #ifdef CONFIG_TEGRA_GK20A_NVHOST | 1659 | #ifdef CONFIG_TEGRA_GK20A_NVHOST |
1660 | static int set_syncpt_ro_map_gpu_va_locked(struct vm_gk20a *vm) | ||
1661 | { | ||
1662 | struct gk20a *g = gk20a_from_vm(vm); | ||
1663 | |||
1664 | if (vm->syncpt_ro_map_gpu_va) | ||
1665 | return 0; | ||
1666 | |||
1667 | vm->syncpt_ro_map_gpu_va = nvgpu_gmmu_map(vm, | ||
1668 | &g->syncpt_mem, g->syncpt_unit_size, | ||
1669 | 0, gk20a_mem_flag_read_only, | ||
1670 | false, APERTURE_SYSMEM); | ||
1671 | |||
1672 | if (!vm->syncpt_ro_map_gpu_va) { | ||
1673 | nvgpu_err(g, "failed to ro map syncpt buffer"); | ||
1674 | return -ENOMEM; | ||
1675 | } | ||
1676 | |||
1677 | return 0; | ||
1678 | } | ||
1679 | |||
1660 | int gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c, | 1680 | int gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c, |
1661 | u32 syncpt_id, struct nvgpu_mem *syncpt_buf) | 1681 | u32 syncpt_id, struct nvgpu_mem *syncpt_buf) |
1662 | { | 1682 | { |
1663 | u32 nr_pages; | 1683 | u32 nr_pages; |
1664 | int err = 0; | 1684 | int err = 0; |
1665 | struct gk20a *g = c->g; | 1685 | struct gk20a *g = c->g; |
1666 | struct vm_gk20a *vm = c->vm; | ||
1667 | 1686 | ||
1668 | /* | 1687 | /* |
1669 | * Add ro map for complete sync point shim range in vm | 1688 | * Add ro map for complete sync point shim range in vm |
1670 | * All channels sharing same vm will share same ro mapping. | 1689 | * All channels sharing same vm will share same ro mapping. |
1671 | * Create rw map for current channel sync point | 1690 | * Create rw map for current channel sync point |
1672 | */ | 1691 | */ |
1673 | if (!vm->syncpt_ro_map_gpu_va) { | 1692 | nvgpu_mutex_acquire(&c->vm->syncpt_ro_map_lock); |
1674 | vm->syncpt_ro_map_gpu_va = nvgpu_gmmu_map(c->vm, | 1693 | err = set_syncpt_ro_map_gpu_va_locked(c->vm); |
1675 | &g->syncpt_mem, g->syncpt_unit_size, | 1694 | nvgpu_mutex_release(&c->vm->syncpt_ro_map_lock); |
1676 | 0, gk20a_mem_flag_read_only, | 1695 | if (err) |
1677 | false, APERTURE_SYSMEM); | 1696 | return err; |
1678 | |||
1679 | if (!vm->syncpt_ro_map_gpu_va) { | ||
1680 | nvgpu_err(g, "failed to ro map syncpt buffer"); | ||
1681 | nvgpu_dma_free(g, &g->syncpt_mem); | ||
1682 | err = -ENOMEM; | ||
1683 | } | ||
1684 | } | ||
1685 | 1697 | ||
1686 | nr_pages = DIV_ROUND_UP(g->syncpt_size, PAGE_SIZE); | 1698 | nr_pages = DIV_ROUND_UP(g->syncpt_size, PAGE_SIZE); |
1687 | __nvgpu_mem_create_from_phys(g, syncpt_buf, | 1699 | __nvgpu_mem_create_from_phys(g, syncpt_buf, |
@@ -1707,6 +1719,24 @@ void gv11b_fifo_free_syncpt_buf(struct channel_gk20a *c, | |||
1707 | nvgpu_dma_free(c->g, syncpt_buf); | 1719 | nvgpu_dma_free(c->g, syncpt_buf); |
1708 | } | 1720 | } |
1709 | 1721 | ||
1722 | int gv11b_fifo_get_sync_ro_map(struct vm_gk20a *vm, | ||
1723 | u64 *base_gpuva, u32 *sync_size) | ||
1724 | { | ||
1725 | struct gk20a *g = gk20a_from_vm(vm); | ||
1726 | int err; | ||
1727 | |||
1728 | nvgpu_mutex_acquire(&vm->syncpt_ro_map_lock); | ||
1729 | err = set_syncpt_ro_map_gpu_va_locked(vm); | ||
1730 | nvgpu_mutex_release(&vm->syncpt_ro_map_lock); | ||
1731 | if (err) | ||
1732 | return err; | ||
1733 | |||
1734 | *base_gpuva = vm->syncpt_ro_map_gpu_va; | ||
1735 | *sync_size = g->syncpt_size; | ||
1736 | |||
1737 | return 0; | ||
1738 | } | ||
1739 | |||
1710 | void gv11b_fifo_add_syncpt_wait_cmd(struct gk20a *g, | 1740 | void gv11b_fifo_add_syncpt_wait_cmd(struct gk20a *g, |
1711 | struct priv_cmd_entry *cmd, u32 off, | 1741 | struct priv_cmd_entry *cmd, u32 off, |
1712 | u32 id, u32 thresh, u64 gpu_va_base) | 1742 | u32 id, u32 thresh, u64 gpu_va_base) |
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h index fc1ddf83..c0e6e5cd 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GV11B Fifo | 2 | * GV11B Fifo |
3 | * | 3 | * |
4 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -102,6 +102,8 @@ int gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c, | |||
102 | u32 syncpt_id, struct nvgpu_mem *syncpt_buf); | 102 | u32 syncpt_id, struct nvgpu_mem *syncpt_buf); |
103 | void gv11b_fifo_free_syncpt_buf(struct channel_gk20a *c, | 103 | void gv11b_fifo_free_syncpt_buf(struct channel_gk20a *c, |
104 | struct nvgpu_mem *syncpt_buf); | 104 | struct nvgpu_mem *syncpt_buf); |
105 | int gv11b_fifo_get_sync_ro_map(struct vm_gk20a *vm, | ||
106 | u64 *base_gpuva, u32 *sync_size); | ||
105 | void gv11b_fifo_add_syncpt_wait_cmd(struct gk20a *g, | 107 | void gv11b_fifo_add_syncpt_wait_cmd(struct gk20a *g, |
106 | struct priv_cmd_entry *cmd, u32 off, | 108 | struct priv_cmd_entry *cmd, u32 off, |
107 | u32 id, u32 thresh, u64 gpu_va_base); | 109 | u32 id, u32 thresh, u64 gpu_va_base); |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 91d80080..72537b44 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -534,6 +534,7 @@ static const struct gpu_ops gv11b_ops = { | |||
534 | .get_syncpt_wait_cmd_size = gv11b_fifo_get_syncpt_wait_cmd_size, | 534 | .get_syncpt_wait_cmd_size = gv11b_fifo_get_syncpt_wait_cmd_size, |
535 | .add_syncpt_incr_cmd = gv11b_fifo_add_syncpt_incr_cmd, | 535 | .add_syncpt_incr_cmd = gv11b_fifo_add_syncpt_incr_cmd, |
536 | .get_syncpt_incr_cmd_size = gv11b_fifo_get_syncpt_incr_cmd_size, | 536 | .get_syncpt_incr_cmd_size = gv11b_fifo_get_syncpt_incr_cmd_size, |
537 | .get_sync_ro_map = gv11b_fifo_get_sync_ro_map, | ||
537 | #endif | 538 | #endif |
538 | .resetup_ramfc = NULL, | 539 | .resetup_ramfc = NULL, |
539 | .device_info_fault_id = top_device_info_data_fault_id_enum_v, | 540 | .device_info_fault_id = top_device_info_data_fault_id_enum_v, |