gpu: nvgpu: HAL-ify pmm type broadcast values

The PMM type-specific broadcast->unicast expansion calculation
was using incorrect values.  This caused the invalid register
accesses to be generated.

This change HAL-ifies the values, so that the expansion will be
performed correctly.

Bug 200454109

Change-Id: I96c15de27b5e16e4db2e788fd98e6bf7d6e7d564
Signed-off-by: Matthew Braun <matthewb@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1921717
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

3 files changed, 33 insertions, 16 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index bb76178e..2e1b4664 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -4920,14 +4920,17 @@ int gr_gv11b_create_priv_addr_table(struct gk20a *g,
                 u32 offset = 0;
 
                 if (broadcast_flags & PRI_BROADCAST_FLAGS_PMM_GPCGS_GPCTPCA) {
-                        pmm_domain_start = NV_PERF_PMMGPCTPCA_DOMAIN_START;
-                        num_domains = NV_PERF_PMMGPC_NUM_DOMAINS;
+                        pmm_domain_start = nvgpu_get_litter_value(g,
+                                GPU_LIT_PERFMON_PMMGPCTPCA_DOMAIN_START);
+                        num_domains = nvgpu_get_litter_value(g,
+                                GPU_LIT_PERFMON_PMMGPCTPC_DOMAIN_COUNT);
                         offset = PRI_PMMGS_OFFSET_MASK(addr);
                 } else if (broadcast_flags &
                                 PRI_BROADCAST_FLAGS_PMM_GPCGS_GPCTPCB) {
-                        pmm_domain_start = NV_PERF_PMMGPCTPCA_DOMAIN_START +
-                                           NV_PERF_PMMGPC_NUM_DOMAINS;
-                        num_domains = NV_PERF_PMMGPC_NUM_DOMAINS;
+                        pmm_domain_start = nvgpu_get_litter_value(g,
+                                GPU_LIT_PERFMON_PMMGPCTPCB_DOMAIN_START);
+                        num_domains = nvgpu_get_litter_value(g,
+                                GPU_LIT_PERFMON_PMMGPCTPC_DOMAIN_COUNT);
                         offset = PRI_PMMGS_OFFSET_MASK(addr);
                 } else if (broadcast_flags & PRI_BROADCAST_FLAGS_PMM_GPCS) {
                         pmm_domain_start = (addr -
@@ -4969,15 +4972,15 @@ int gr_gv11b_create_priv_addr_table(struct gk20a *g,
                 gr_gv11b_split_pmm_fbp_broadcast_address(g,
                         PRI_PMMGS_OFFSET_MASK(addr),
                         priv_addr_table, &t,
-                        NV_PERF_PMMFBP_LTC_DOMAIN_START,
-                        NV_PERF_PMMFBP_LTC_NUM_DOMAINS);
+                        nvgpu_get_litter_value(g, GPU_LIT_PERFMON_PMMFBP_LTC_DOMAIN_START),
+                        nvgpu_get_litter_value(g, GPU_LIT_PERFMON_PMMFBP_LTC_DOMAIN_COUNT));
         } else if ((addr_type == CTXSW_ADDR_TYPE_ROP) &&
                    (broadcast_flags & PRI_BROADCAST_FLAGS_PMM_FBPGS_ROP)) {
                 gr_gv11b_split_pmm_fbp_broadcast_address(g,
                         PRI_PMMGS_OFFSET_MASK(addr),
                         priv_addr_table, &t,
-                        NV_PERF_PMMFBP_ROP_DOMAIN_START,
-                        NV_PERF_PMMFBP_ROP_NUM_DOMAINS);
+                        nvgpu_get_litter_value(g, GPU_LIT_PERFMON_PMMFBP_ROP_DOMAIN_START),
+                        nvgpu_get_litter_value(g, GPU_LIT_PERFMON_PMMFBP_ROP_DOMAIN_COUNT));
         } else if ((addr_type == CTXSW_ADDR_TYPE_FBP) &&
                    (broadcast_flags & PRI_BROADCAST_FLAGS_PMM_FBPS)) {
                 u32 domain_start;
diff --git a/drivers/gpu/nvgpu/gv11b/gr_pri_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_pri_gv11b.h
index 78658bf8..c71f4c9c 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_pri_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/gr_pri_gv11b.h
@@ -37,13 +37,6 @@
 #define NV_PERF_PMMGPC_GPCS                  0x00278000
 #define NV_PERF_PMMFBP_FBPS                  0x0027C000
 
-#define NV_PERF_PMMGPCTPCA_DOMAIN_START      2
-#define NV_PERF_PMMFBP_LTC_DOMAIN_START      2
-#define NV_PERF_PMMFBP_ROP_DOMAIN_START      6
-#define NV_PERF_PMMGPC_NUM_DOMAINS           7
-#define NV_PERF_PMMFBP_LTC_NUM_DOMAINS       4
-#define NV_PERF_PMMFBP_ROP_NUM_DOMAINS       2
-
 #define PRI_PMMGS_ADDR_WIDTH                 9
 #define PRI_PMMS_ADDR_WIDTH                  14
 
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index 468abdd1..cf6a7e2c 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -223,6 +223,27 @@ u32 gv11b_get_litter_value(struct gk20a *g, int value)
         case GPU_LIT_GPC_PRIV_STRIDE:
                 ret = proj_gpc_priv_stride_v();
                 break;
+        case GPU_LIT_PERFMON_PMMGPCTPCA_DOMAIN_START:
+                ret = 2;
+                break;
+        case GPU_LIT_PERFMON_PMMGPCTPCB_DOMAIN_START:
+                ret = 6;
+                break;
+        case GPU_LIT_PERFMON_PMMGPCTPC_DOMAIN_COUNT:
+                ret = 4;
+                break;
+        case GPU_LIT_PERFMON_PMMFBP_LTC_DOMAIN_START:
+                ret = 1;
+                break;
+        case GPU_LIT_PERFMON_PMMFBP_LTC_DOMAIN_COUNT:
+                ret = 2;
+                break;
+        case GPU_LIT_PERFMON_PMMFBP_ROP_DOMAIN_START:
+                ret = 3;
+                break;
+        case GPU_LIT_PERFMON_PMMFBP_ROP_DOMAIN_COUNT:
+                ret = 2;
+                break;
         default:
                 nvgpu_err(g, "Missing definition %d", value);
                 BUG();