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authorVinod G <vinodg@nvidia.com>2018-07-10 19:13:03 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-07-19 03:06:43 -0400
commitd859c5f4a03b975dc493f72a35016e83adad279a (patch)
treee7a1242a1d130a726456cf3a928a34941aad98f4 /drivers/gpu/nvgpu/gv11b
parent74e1a11d840b3d7411b380c2e4e4c99126ea32a5 (diff)
nvgpu: gv11b: Rearrange gr function
Moved gv11b_detect_ecc_enabled_units function from gv11b.c to gr_gv11b.c, as this is being used only in gr_gv11b file. In order to avoid GR code touching fuse registers, as it need to include fuse HW headers in GR code, introduced two fuse HALs which are being called from GR code. is_opt_ecc_enable for checking whether ecc enable bit is set in fuse register and is_opt_feature_overide_disable for checking whether feature override disable bit is set in fuse register. Initialized fuse HAL functions for chips that make use of those HAL functions. JIRA NVGPU-615 Change-Id: Iafe5a3940bb19cb3da51e270403450b63c2f67a3 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1775564 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b')
-rw-r--r--drivers/gpu/nvgpu/gv11b/gr_gv11b.c116
-rw-r--r--drivers/gpu/nvgpu/gv11b/gv11b.c121
-rw-r--r--drivers/gpu/nvgpu/gv11b/gv11b.h1
-rw-r--r--drivers/gpu/nvgpu/gv11b/hal_gv11b.c3
4 files changed, 118 insertions, 123 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index 6ceaa47a..d3fe5f65 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -4488,11 +4488,125 @@ static int gr_gv11b_ecc_scrub_sm_icahe(struct gk20a *g)
4488 scrub_mask, scrub_done); 4488 scrub_mask, scrub_done);
4489} 4489}
4490 4490
4491static void gr_gv11b_detect_ecc_enabled_units(struct gk20a *g)
4492{
4493 bool opt_ecc_en = g->ops.fuse.is_opt_ecc_enable(g);
4494 bool opt_feature_fuses_override_disable =
4495 g->ops.fuse.is_opt_feature_override_disable(g);
4496 u32 fecs_feature_override_ecc =
4497 gk20a_readl(g,
4498 gr_fecs_feature_override_ecc_r());
4499
4500 if (opt_feature_fuses_override_disable) {
4501 if (opt_ecc_en) {
4502 __nvgpu_set_enabled(g,
4503 NVGPU_ECC_ENABLED_SM_LRF, true);
4504 __nvgpu_set_enabled(g,
4505 NVGPU_ECC_ENABLED_SM_L1_DATA, true);
4506 __nvgpu_set_enabled(g,
4507 NVGPU_ECC_ENABLED_SM_L1_TAG, true);
4508 __nvgpu_set_enabled(g,
4509 NVGPU_ECC_ENABLED_SM_ICACHE, true);
4510 __nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_LTC, true);
4511 __nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_SM_CBU, true);
4512 }
4513 } else {
4514 /* SM LRF */
4515 if (gr_fecs_feature_override_ecc_sm_lrf_override_v(
4516 fecs_feature_override_ecc) == 1U) {
4517 if (gr_fecs_feature_override_ecc_sm_lrf_v(
4518 fecs_feature_override_ecc) == 1U) {
4519 __nvgpu_set_enabled(g,
4520 NVGPU_ECC_ENABLED_SM_LRF, true);
4521 }
4522 } else {
4523 if (opt_ecc_en) {
4524 __nvgpu_set_enabled(g,
4525 NVGPU_ECC_ENABLED_SM_LRF, true);
4526 }
4527 }
4528 /* SM L1 DATA*/
4529 if (gr_fecs_feature_override_ecc_sm_l1_data_override_v(
4530 fecs_feature_override_ecc) == 1U) {
4531 if (gr_fecs_feature_override_ecc_sm_l1_data_v(
4532 fecs_feature_override_ecc) == 1U) {
4533 __nvgpu_set_enabled(g,
4534 NVGPU_ECC_ENABLED_SM_L1_DATA, true);
4535 }
4536 } else {
4537 if (opt_ecc_en) {
4538 __nvgpu_set_enabled(g,
4539 NVGPU_ECC_ENABLED_SM_L1_DATA, true);
4540 }
4541 }
4542 /* SM L1 TAG*/
4543 if (gr_fecs_feature_override_ecc_sm_l1_tag_override_v(
4544 fecs_feature_override_ecc) == 1U) {
4545 if (gr_fecs_feature_override_ecc_sm_l1_tag_v(
4546 fecs_feature_override_ecc) == 1U) {
4547 __nvgpu_set_enabled(g,
4548 NVGPU_ECC_ENABLED_SM_L1_TAG, true);
4549 }
4550 } else {
4551 if (opt_ecc_en) {
4552 __nvgpu_set_enabled(g,
4553 NVGPU_ECC_ENABLED_SM_L1_TAG, true);
4554 }
4555 }
4556 /* SM ICACHE*/
4557 if ((gr_fecs_feature_override_ecc_1_sm_l0_icache_override_v(
4558 fecs_feature_override_ecc) == 1U) &&
4559 (gr_fecs_feature_override_ecc_1_sm_l1_icache_override_v(
4560 fecs_feature_override_ecc) == 1U)) {
4561 if ((gr_fecs_feature_override_ecc_1_sm_l0_icache_v(
4562 fecs_feature_override_ecc) == 1U) &&
4563 (gr_fecs_feature_override_ecc_1_sm_l1_icache_v(
4564 fecs_feature_override_ecc) == 1U)) {
4565 __nvgpu_set_enabled(g,
4566 NVGPU_ECC_ENABLED_SM_ICACHE, true);
4567 }
4568 } else {
4569 if (opt_ecc_en) {
4570 __nvgpu_set_enabled(g,
4571 NVGPU_ECC_ENABLED_SM_ICACHE, true);
4572 }
4573 }
4574 /* LTC */
4575 if (gr_fecs_feature_override_ecc_ltc_override_v(
4576 fecs_feature_override_ecc) == 1U) {
4577 if (gr_fecs_feature_override_ecc_ltc_v(
4578 fecs_feature_override_ecc) == 1U) {
4579 __nvgpu_set_enabled(g,
4580 NVGPU_ECC_ENABLED_LTC, true);
4581 }
4582 } else {
4583 if (opt_ecc_en) {
4584 __nvgpu_set_enabled(g,
4585 NVGPU_ECC_ENABLED_LTC, true);
4586 }
4587 }
4588 /* SM CBU */
4589 if (gr_fecs_feature_override_ecc_sm_cbu_override_v(
4590 fecs_feature_override_ecc) == 1U) {
4591 if (gr_fecs_feature_override_ecc_sm_cbu_v(
4592 fecs_feature_override_ecc) == 1U) {
4593 __nvgpu_set_enabled(g,
4594 NVGPU_ECC_ENABLED_SM_CBU, true);
4595 }
4596 } else {
4597 if (opt_ecc_en) {
4598 __nvgpu_set_enabled(g,
4599 NVGPU_ECC_ENABLED_SM_CBU, true);
4600 }
4601 }
4602 }
4603}
4604
4491void gr_gv11b_ecc_init_scrub_reg(struct gk20a *g) 4605void gr_gv11b_ecc_init_scrub_reg(struct gk20a *g)
4492{ 4606{
4493 nvgpu_log_fn(g, "ecc srub start "); 4607 nvgpu_log_fn(g, "ecc srub start ");
4494 4608
4495 gv11b_detect_ecc_enabled_units(g); 4609 gr_gv11b_detect_ecc_enabled_units(g);
4496 4610
4497 if (gr_gv11b_ecc_scrub_sm_lrf(g)) 4611 if (gr_gv11b_ecc_scrub_sm_lrf(g))
4498 nvgpu_warn(g, "ECC SCRUB SM LRF Failed"); 4612 nvgpu_warn(g, "ECC SCRUB SM LRF Failed");
diff --git a/drivers/gpu/nvgpu/gv11b/gv11b.c b/drivers/gpu/nvgpu/gv11b/gv11b.c
index 44120498..5d2bfbd7 100644
--- a/drivers/gpu/nvgpu/gv11b/gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gv11b.c
@@ -25,128 +25,7 @@
25#include <nvgpu/enabled.h> 25#include <nvgpu/enabled.h>
26 26
27#include "gk20a/gk20a.h" 27#include "gk20a/gk20a.h"
28#include "gp10b/gp10b.h"
29
30#include "gv11b/gv11b.h" 28#include "gv11b/gv11b.h"
31#include <nvgpu/hw/gv11b/hw_fuse_gv11b.h>
32#include <nvgpu/hw/gv11b/hw_gr_gv11b.h>
33
34void gv11b_detect_ecc_enabled_units(struct gk20a *g)
35{
36 u32 opt_ecc_en = gk20a_readl(g, fuse_opt_ecc_en_r());
37 u32 opt_feature_fuses_override_disable =
38 gk20a_readl(g,
39 fuse_opt_feature_fuses_override_disable_r());
40 u32 fecs_feature_override_ecc =
41 gk20a_readl(g,
42 gr_fecs_feature_override_ecc_r());
43
44 if (opt_feature_fuses_override_disable) {
45 if (opt_ecc_en) {
46 __nvgpu_set_enabled(g,
47 NVGPU_ECC_ENABLED_SM_LRF, true);
48 __nvgpu_set_enabled(g,
49 NVGPU_ECC_ENABLED_SM_L1_DATA, true);
50 __nvgpu_set_enabled(g,
51 NVGPU_ECC_ENABLED_SM_L1_TAG, true);
52 __nvgpu_set_enabled(g,
53 NVGPU_ECC_ENABLED_SM_ICACHE, true);
54 __nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_LTC, true);
55 __nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_SM_CBU, true);
56 }
57 } else {
58 /* SM LRF */
59 if (gr_fecs_feature_override_ecc_sm_lrf_override_v(
60 fecs_feature_override_ecc)) {
61 if (gr_fecs_feature_override_ecc_sm_lrf_v(
62 fecs_feature_override_ecc)) {
63 __nvgpu_set_enabled(g,
64 NVGPU_ECC_ENABLED_SM_LRF, true);
65 }
66 } else {
67 if (opt_ecc_en) {
68 __nvgpu_set_enabled(g,
69 NVGPU_ECC_ENABLED_SM_LRF, true);
70 }
71 }
72 /* SM L1 DATA*/
73 if (gr_fecs_feature_override_ecc_sm_l1_data_override_v(
74 fecs_feature_override_ecc)) {
75 if (gr_fecs_feature_override_ecc_sm_l1_data_v(
76 fecs_feature_override_ecc)) {
77 __nvgpu_set_enabled(g,
78 NVGPU_ECC_ENABLED_SM_L1_DATA, true);
79 }
80 } else {
81 if (opt_ecc_en) {
82 __nvgpu_set_enabled(g,
83 NVGPU_ECC_ENABLED_SM_L1_DATA, true);
84 }
85 }
86 /* SM L1 TAG*/
87 if (gr_fecs_feature_override_ecc_sm_l1_tag_override_v(
88 fecs_feature_override_ecc)) {
89 if (gr_fecs_feature_override_ecc_sm_l1_tag_v(
90 fecs_feature_override_ecc)) {
91 __nvgpu_set_enabled(g,
92 NVGPU_ECC_ENABLED_SM_L1_TAG, true);
93 }
94 } else {
95 if (opt_ecc_en) {
96 __nvgpu_set_enabled(g,
97 NVGPU_ECC_ENABLED_SM_L1_TAG, true);
98 }
99 }
100 /* SM ICACHE*/
101 if (gr_fecs_feature_override_ecc_1_sm_l0_icache_override_v(
102 fecs_feature_override_ecc) &&
103 gr_fecs_feature_override_ecc_1_sm_l1_icache_override_v(
104 fecs_feature_override_ecc)) {
105 if (gr_fecs_feature_override_ecc_1_sm_l0_icache_v(
106 fecs_feature_override_ecc) &&
107 gr_fecs_feature_override_ecc_1_sm_l1_icache_v(
108 fecs_feature_override_ecc)) {
109 __nvgpu_set_enabled(g,
110 NVGPU_ECC_ENABLED_SM_ICACHE, true);
111 }
112 } else {
113 if (opt_ecc_en) {
114 __nvgpu_set_enabled(g,
115 NVGPU_ECC_ENABLED_SM_ICACHE, true);
116 }
117 }
118 /* LTC */
119 if (gr_fecs_feature_override_ecc_ltc_override_v(
120 fecs_feature_override_ecc)) {
121 if (gr_fecs_feature_override_ecc_ltc_v(
122 fecs_feature_override_ecc)) {
123 __nvgpu_set_enabled(g,
124 NVGPU_ECC_ENABLED_LTC, true);
125 }
126 } else {
127 if (opt_ecc_en) {
128 __nvgpu_set_enabled(g,
129 NVGPU_ECC_ENABLED_LTC, true);
130 }
131 }
132 /* SM CBU */
133 if (gr_fecs_feature_override_ecc_sm_cbu_override_v(
134 fecs_feature_override_ecc)) {
135 if (gr_fecs_feature_override_ecc_sm_cbu_v(
136 fecs_feature_override_ecc)) {
137 __nvgpu_set_enabled(g,
138 NVGPU_ECC_ENABLED_SM_CBU, true);
139 }
140 } else {
141 if (opt_ecc_en) {
142 __nvgpu_set_enabled(g,
143 NVGPU_ECC_ENABLED_SM_CBU, true);
144 }
145 }
146 }
147}
148
149
150 29
151int gv11b_init_gpu_characteristics(struct gk20a *g) 30int gv11b_init_gpu_characteristics(struct gk20a *g)
152{ 31{
diff --git a/drivers/gpu/nvgpu/gv11b/gv11b.h b/drivers/gpu/nvgpu/gv11b/gv11b.h
index 17dfa7aa..3d5490e6 100644
--- a/drivers/gpu/nvgpu/gv11b/gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/gv11b.h
@@ -27,7 +27,6 @@
27 27
28#include "gk20a/gk20a.h" 28#include "gk20a/gk20a.h"
29 29
30void gv11b_detect_ecc_enabled_units(struct gk20a *g);
31int gv11b_init_gpu_characteristics(struct gk20a *g); 30int gv11b_init_gpu_characteristics(struct gk20a *g);
32 31
33#endif /* GV11B_H */ 32#endif /* GV11B_H */
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index 325285a6..00367e5b 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -790,6 +790,9 @@ static const struct gpu_ops gv11b_ops = {
790 }, 790 },
791 .fuse = { 791 .fuse = {
792 .check_priv_security = gp10b_fuse_check_priv_security, 792 .check_priv_security = gp10b_fuse_check_priv_security,
793 .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable,
794 .is_opt_feature_override_disable =
795 gp10b_fuse_is_opt_feature_override_disable,
793 }, 796 },
794 .chip_init_gpu_characteristics = gv11b_init_gpu_characteristics, 797 .chip_init_gpu_characteristics = gv11b_init_gpu_characteristics,
795 .get_litter_value = gv11b_get_litter_value, 798 .get_litter_value = gv11b_get_litter_value,
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-07 16:21:33 -0400