diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-09-21 19:24:04 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-11-01 03:00:50 -0400 |
commit | d69e51813a57dfae204daf87767652685117daf1 (patch) | |
tree | a19cd6300aa8c26c4017a50bf14f725c5e137244 /drivers/gpu/nvgpu/gv11b | |
parent | cfba56d20e27cdc591f8a89236dd1423b12754d3 (diff) |
gpu: nvgpu: gv11b: fix faulted channel's id/type
Teardown function should be passed appropriate id and
id_type. E.g. if a channel is marked as tsg, channel teardown/rc
function should be passed it's tsgid as id and type_tsg as
id_type
Bug 200277163
Change-Id: I2e83561c03d515fac28cbb8ce75a9f2c7bf746ac
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1557296
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index 9301ebc6..75045800 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c | |||
@@ -1376,6 +1376,7 @@ static void gv11b_fb_handle_mmu_fault_common(struct gk20a *g, | |||
1376 | unsigned int id_type; | 1376 | unsigned int id_type; |
1377 | u32 num_lce, act_eng_bitmask = 0; | 1377 | u32 num_lce, act_eng_bitmask = 0; |
1378 | int err = 0; | 1378 | int err = 0; |
1379 | u32 id = ((u32)~0); | ||
1379 | 1380 | ||
1380 | if (!mmfault->valid) | 1381 | if (!mmfault->valid) |
1381 | return; | 1382 | return; |
@@ -1417,10 +1418,13 @@ static void gv11b_fb_handle_mmu_fault_common(struct gk20a *g, | |||
1417 | nvgpu_log(g, gpu_dbg_intr, "UNBOUND INST BLOCK MMU FAULT"); | 1418 | nvgpu_log(g, gpu_dbg_intr, "UNBOUND INST BLOCK MMU FAULT"); |
1418 | 1419 | ||
1419 | } else if (mmfault->refch) { | 1420 | } else if (mmfault->refch) { |
1420 | if (gk20a_is_channel_marked_as_tsg(mmfault->refch)) | 1421 | if (gk20a_is_channel_marked_as_tsg(mmfault->refch)) { |
1422 | id = mmfault->refch->tsgid; | ||
1421 | id_type = ID_TYPE_TSG; | 1423 | id_type = ID_TYPE_TSG; |
1422 | else | 1424 | } else { |
1425 | id = mmfault->chid; | ||
1423 | id_type = ID_TYPE_CHANNEL; | 1426 | id_type = ID_TYPE_CHANNEL; |
1427 | } | ||
1424 | } else { | 1428 | } else { |
1425 | id_type = ID_TYPE_UNKNOWN; | 1429 | id_type = ID_TYPE_UNKNOWN; |
1426 | } | 1430 | } |
@@ -1428,7 +1432,7 @@ static void gv11b_fb_handle_mmu_fault_common(struct gk20a *g, | |||
1428 | act_eng_bitmask = BIT(mmfault->faulted_engine); | 1432 | act_eng_bitmask = BIT(mmfault->faulted_engine); |
1429 | 1433 | ||
1430 | g->ops.fifo.teardown_ch_tsg(g, act_eng_bitmask, | 1434 | g->ops.fifo.teardown_ch_tsg(g, act_eng_bitmask, |
1431 | mmfault->chid, id_type, RC_TYPE_MMU_FAULT, mmfault); | 1435 | id, id_type, RC_TYPE_MMU_FAULT, mmfault); |
1432 | } else { | 1436 | } else { |
1433 | err = gv11b_fb_fix_page_fault(g, mmfault); | 1437 | err = gv11b_fb_fix_page_fault(g, mmfault); |
1434 | if (err) { | 1438 | if (err) { |