diff options
author | Deepak Goyal <dgoyal@nvidia.com> | 2018-07-16 01:40:23 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-07-24 02:52:39 -0400 |
commit | d3b8415948de8c9ffe2f2fa66340dd7e71a894e6 (patch) | |
tree | 328970819ace31fae3bf3bc27376121330064db9 /drivers/gpu/nvgpu/gv11b | |
parent | 2df33e32e40eb2c8e025f8d27396d9b5cdb3ac11 (diff) |
gpu: nvgpu: tpc powergating through sysfs
- adds static tpc-powergating through sysfs.
- active tpc count will remain till the GPU/systems is not booted again.
- tpc_pg_mask can be written only after GPU probe finishes and
GPU boot is triggered.
Note:
To be able to use this feature, we need to change boot/init
scripts of the OS(used with nvgpu driver) to write to sysfs nodes before
posting discover image size query to FECS.
Bug 200406784
Change-Id: Id749c7a617422c625f77d0c1a9aada2eb960c4d0
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1742422
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 40 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 |
3 files changed, 42 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index c2f47a20..51588f1f 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -58,6 +58,7 @@ | |||
58 | #include <nvgpu/hw/gv11b/hw_pbdma_gv11b.h> | 58 | #include <nvgpu/hw/gv11b/hw_pbdma_gv11b.h> |
59 | #include <nvgpu/hw/gv11b/hw_therm_gv11b.h> | 59 | #include <nvgpu/hw/gv11b/hw_therm_gv11b.h> |
60 | #include <nvgpu/hw/gv11b/hw_perf_gv11b.h> | 60 | #include <nvgpu/hw/gv11b/hw_perf_gv11b.h> |
61 | #include <nvgpu/hw/gv11b/hw_fuse_gv11b.h> | ||
61 | 62 | ||
62 | #define GFXP_WFI_TIMEOUT_COUNT_IN_USEC_DEFAULT 100 | 63 | #define GFXP_WFI_TIMEOUT_COUNT_IN_USEC_DEFAULT 100 |
63 | 64 | ||
@@ -71,6 +72,16 @@ | |||
71 | */ | 72 | */ |
72 | #define GR_TPCS_INFO_FOR_MAPREGISTER 6 | 73 | #define GR_TPCS_INFO_FOR_MAPREGISTER 6 |
73 | 74 | ||
75 | /* | ||
76 | * There are 4 TPCs in GV11b ranging from TPC0 to TPC3 | ||
77 | * There are two PES in GV11b each controlling two TPCs | ||
78 | * PES0 is linked to TPC0 & TPC2 | ||
79 | * PES1 is linked to TPC1 & TPC3 | ||
80 | */ | ||
81 | #define TPC_MASK_FOR_PESID_0 (u32) 0x5 | ||
82 | #define TPC_MASK_FOR_PESID_1 (u32) 0xa | ||
83 | |||
84 | |||
74 | bool gr_gv11b_is_valid_class(struct gk20a *g, u32 class_num) | 85 | bool gr_gv11b_is_valid_class(struct gk20a *g, u32 class_num) |
75 | { | 86 | { |
76 | bool valid = false; | 87 | bool valid = false; |
@@ -117,6 +128,35 @@ bool gr_gv11b_is_valid_gfx_class(struct gk20a *g, u32 class_num) | |||
117 | return valid; | 128 | return valid; |
118 | } | 129 | } |
119 | 130 | ||
131 | void gr_gv11b_powergate_tpc(struct gk20a *g) | ||
132 | { | ||
133 | u32 tpc_pg_status = gk20a_readl(g, fuse_status_opt_tpc_gpc_r(0)); | ||
134 | |||
135 | if (tpc_pg_status == g->tpc_pg_mask) { | ||
136 | nvgpu_info(g, "TPC-PG mask and TPC-PG status is same"); | ||
137 | return; | ||
138 | } | ||
139 | |||
140 | gk20a_writel(g, fuse_ctrl_opt_tpc_gpc_r(0), (g->tpc_pg_mask)); | ||
141 | |||
142 | do { | ||
143 | tpc_pg_status = gk20a_readl(g, fuse_status_opt_tpc_gpc_r(0)); | ||
144 | } while (tpc_pg_status != g->tpc_pg_mask); | ||
145 | |||
146 | gk20a_writel(g, gr_fe_tpc_pesmask_r(), gr_fe_tpc_pesmask_req_send_f() | | ||
147 | gr_fe_tpc_pesmask_action_write_f() | | ||
148 | gr_fe_tpc_pesmask_pesid_f(0) | | ||
149 | gr_fe_tpc_pesmask_gpcid_f(0) | | ||
150 | ((~g->tpc_pg_mask & (u32) 0xf) & TPC_MASK_FOR_PESID_0)); | ||
151 | gk20a_writel(g, gr_fe_tpc_pesmask_r(), gr_fe_tpc_pesmask_req_send_f() | | ||
152 | gr_fe_tpc_pesmask_action_write_f() | | ||
153 | gr_fe_tpc_pesmask_pesid_f(1) | | ||
154 | gr_fe_tpc_pesmask_gpcid_f(0) | | ||
155 | ((~g->tpc_pg_mask & (u32) 0xf) & TPC_MASK_FOR_PESID_1)); | ||
156 | |||
157 | return; | ||
158 | } | ||
159 | |||
120 | bool gr_gv11b_is_valid_compute_class(struct gk20a *g, u32 class_num) | 160 | bool gr_gv11b_is_valid_compute_class(struct gk20a *g, u32 class_num) |
121 | { | 161 | { |
122 | bool valid = false; | 162 | bool valid = false; |
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index a8dbd3a8..f799ccfe 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h | |||
@@ -250,4 +250,5 @@ int gr_gv11b_create_priv_addr_table(struct gk20a *g, | |||
250 | u32 *priv_addr_table, | 250 | u32 *priv_addr_table, |
251 | u32 *num_registers); | 251 | u32 *num_registers); |
252 | u32 gr_gv11b_get_nonpes_aware_tpc(struct gk20a *g, u32 gpc, u32 tpc); | 252 | u32 gr_gv11b_get_nonpes_aware_tpc(struct gk20a *g, u32 gpc, u32 tpc); |
253 | void gr_gv11b_powergate_tpc(struct gk20a *g); | ||
253 | #endif | 254 | #endif |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index d479fef8..08c3097e 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -294,6 +294,7 @@ static const struct gpu_ops gv11b_ops = { | |||
294 | .init_ctx_state = gr_gp10b_init_ctx_state, | 294 | .init_ctx_state = gr_gp10b_init_ctx_state, |
295 | .alloc_gr_ctx = gr_gp10b_alloc_gr_ctx, | 295 | .alloc_gr_ctx = gr_gp10b_alloc_gr_ctx, |
296 | .free_gr_ctx = gr_gk20a_free_gr_ctx, | 296 | .free_gr_ctx = gr_gk20a_free_gr_ctx, |
297 | .powergate_tpc = gr_gv11b_powergate_tpc, | ||
297 | .update_ctxsw_preemption_mode = | 298 | .update_ctxsw_preemption_mode = |
298 | gr_gv11b_update_ctxsw_preemption_mode, | 299 | gr_gv11b_update_ctxsw_preemption_mode, |
299 | .dump_gr_regs = gr_gv11b_dump_gr_status_regs, | 300 | .dump_gr_regs = gr_gv11b_dump_gr_status_regs, |