diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-07-09 17:00:24 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-07-10 02:34:19 -0400 |
commit | cc940da42f34568d6327ee20653725d11b1a3258 (patch) | |
tree | 4d32ca9aeecaf149848af68550ea5ab64b76cfd8 /drivers/gpu/nvgpu/gv11b | |
parent | d9ee7aff0455ad79caf395cedd53c3e092d2538c (diff) |
gpu: nvgpu: gv11b: enable and handle mpc exception
Implement gr ops to handle MPC exception triggered per TPC
JIRA GPUT19X-69
Change-Id: Ia92b1d51ad896116b25d71e07ed26f1539475be8
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1515915
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 40 |
1 files changed, 37 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index d61506c2..2c3b0820 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -885,7 +885,8 @@ static void gr_gv11b_enable_gpc_exceptions(struct gk20a *g) | |||
885 | u32 tpc_mask; | 885 | u32 tpc_mask; |
886 | 886 | ||
887 | gk20a_writel(g, gr_gpcs_tpcs_tpccs_tpc_exception_en_r(), | 887 | gk20a_writel(g, gr_gpcs_tpcs_tpccs_tpc_exception_en_r(), |
888 | gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f()); | 888 | gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f() | |
889 | gr_gpcs_tpcs_tpccs_tpc_exception_en_mpc_enabled_f()); | ||
889 | 890 | ||
890 | tpc_mask = | 891 | tpc_mask = |
891 | gr_gpcs_gpccs_gpc_exception_en_tpc_f((1 << gr->tpc_count) - 1); | 892 | gr_gpcs_gpccs_gpc_exception_en_tpc_f((1 << gr->tpc_count) - 1); |
@@ -2973,13 +2974,16 @@ static void gv11b_gr_resume_all_sms(struct gk20a *g) | |||
2973 | static int gv11b_gr_resume_from_pause(struct gk20a *g) | 2974 | static int gv11b_gr_resume_from_pause(struct gk20a *g) |
2974 | { | 2975 | { |
2975 | int err = 0; | 2976 | int err = 0; |
2977 | u32 reg_val; | ||
2976 | 2978 | ||
2977 | /* Clear the pause mask to tell the GPU we want to resume everyone */ | 2979 | /* Clear the pause mask to tell the GPU we want to resume everyone */ |
2978 | gk20a_writel(g, gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_0_r(), 0); | 2980 | gk20a_writel(g, gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_0_r(), 0); |
2979 | 2981 | ||
2980 | /* explicitly re-enable forwarding of SM interrupts upon any resume */ | 2982 | /* explicitly re-enable forwarding of SM interrupts upon any resume */ |
2981 | gk20a_writel(g, gr_gpcs_tpcs_tpccs_tpc_exception_en_r(), | 2983 | reg_val = gk20a_readl(g, gr_gpc0_tpc0_tpccs_tpc_exception_en_r()); |
2982 | gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f()); | 2984 | reg_val |= gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(); |
2985 | |||
2986 | gk20a_writel(g, gr_gpcs_tpcs_tpccs_tpc_exception_en_r(), reg_val); | ||
2983 | 2987 | ||
2984 | g->ops.gr.resume_all_sms(g); | 2988 | g->ops.gr.resume_all_sms(g); |
2985 | 2989 | ||
@@ -3198,6 +3202,34 @@ static void gv11b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, | |||
3198 | offset)); | 3202 | offset)); |
3199 | } | 3203 | } |
3200 | 3204 | ||
3205 | static int gr_gv11b_handle_tpc_mpc_exception(struct gk20a *g, | ||
3206 | u32 gpc, u32 tpc, bool *post_event) | ||
3207 | { | ||
3208 | u32 esr; | ||
3209 | u32 offset = gk20a_gr_gpc_offset(g, gpc) + gk20a_gr_tpc_offset(g, tpc); | ||
3210 | u32 tpc_exception = gk20a_readl(g, gr_gpc0_tpc0_tpccs_tpc_exception_r() | ||
3211 | + offset); | ||
3212 | |||
3213 | if (!(tpc_exception & gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m())) | ||
3214 | return 0; | ||
3215 | |||
3216 | nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg, | ||
3217 | "GPC%d TPC%d MPC exception", gpc, tpc); | ||
3218 | |||
3219 | esr = gk20a_readl(g, gr_gpc0_tpc0_mpc_hww_esr_r() + offset); | ||
3220 | nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg, "mpc hww esr 0x%08x", esr); | ||
3221 | |||
3222 | esr = gk20a_readl(g, gr_gpc0_tpc0_mpc_hww_esr_info_r() + offset); | ||
3223 | nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg, | ||
3224 | "mpc hww esr info: veid 0x%08x", | ||
3225 | gr_gpc0_tpc0_mpc_hww_esr_info_veid_v(esr)); | ||
3226 | |||
3227 | gk20a_writel(g, gr_gpc0_tpc0_mpc_hww_esr_r() + offset, | ||
3228 | gr_gpc0_tpc0_mpc_hww_esr_reset_trigger_f()); | ||
3229 | |||
3230 | return 0; | ||
3231 | } | ||
3232 | |||
3201 | void gv11b_init_gr(struct gpu_ops *gops) | 3233 | void gv11b_init_gr(struct gpu_ops *gops) |
3202 | { | 3234 | { |
3203 | gp10b_init_gr(gops); | 3235 | gp10b_init_gr(gops); |
@@ -3280,4 +3312,6 @@ void gv11b_init_gr(struct gpu_ops *gops) | |||
3280 | gops->gr.clear_sm_hww = gv11b_gr_clear_sm_hww; | 3312 | gops->gr.clear_sm_hww = gv11b_gr_clear_sm_hww; |
3281 | gops->gr.handle_tpc_sm_ecc_exception = | 3313 | gops->gr.handle_tpc_sm_ecc_exception = |
3282 | gr_gv11b_handle_tpc_sm_ecc_exception; | 3314 | gr_gv11b_handle_tpc_sm_ecc_exception; |
3315 | gops->gr.handle_tpc_mpc_exception = | ||
3316 | gr_gv11b_handle_tpc_mpc_exception; | ||
3283 | } | 3317 | } |