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authorScott Long <scottl@nvidia.com>2018-08-23 13:55:04 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-08-30 23:11:22 -0400
commitbc6625b9b2a2e5ef05cedf0888c28819d3c3f412 (patch)
treeab2dad9f15885ff4b3ae698ea457d4b6d6eed4fc /drivers/gpu/nvgpu/gv11b
parentcded55940e6a8d616ef9cc62cacb537a7a2ef55a (diff)
gpu: nvgpu: fix zbc MISRA 10.1 violations
The gr_gk20a_add_zbc() routine returns a signed error (errno) status value. Current callers of this function use a bitwise OR to collect the returned error status values to generate a single value to return. Bitwise OR on signed status values is flagged as a violation of MISRA Rule 10.1 (not to mention that in this case it potentially results in a garbage return value). To eliminate such violations this change modifies the following routines to fail immediately on the first error from a call to gr_gk20a_add_zbc(): * gr_gk20a_load_zbc_default_table() * gr_gv11b_load_stencil_default_tbl() JIRA NVGPU-650 Change-Id: If733c1bb0e05943ff5d0355de729133c89233583 Signed-off-by: Scott Long <scottl@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1805501 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b')
-rw-r--r--drivers/gpu/nvgpu/gv11b/gr_gv11b.c27
1 files changed, 17 insertions, 10 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index 8b3253a1..296d8e90 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -1121,7 +1121,7 @@ int gr_gv11b_load_stencil_default_tbl(struct gk20a *g,
1121 struct gr_gk20a *gr) 1121 struct gr_gk20a *gr)
1122{ 1122{
1123 struct zbc_entry zbc_val; 1123 struct zbc_entry zbc_val;
1124 u32 err; 1124 int err;
1125 1125
1126 /* load default stencil table */ 1126 /* load default stencil table */
1127 zbc_val.type = GV11B_ZBC_TYPE_STENCIL; 1127 zbc_val.type = GV11B_ZBC_TYPE_STENCIL;
@@ -1129,23 +1129,30 @@ int gr_gv11b_load_stencil_default_tbl(struct gk20a *g,
1129 zbc_val.depth = 0x0; 1129 zbc_val.depth = 0x0;
1130 zbc_val.format = ZBC_STENCIL_CLEAR_FMT_U8; 1130 zbc_val.format = ZBC_STENCIL_CLEAR_FMT_U8;
1131 err = gr_gk20a_add_zbc(g, gr, &zbc_val); 1131 err = gr_gk20a_add_zbc(g, gr, &zbc_val);
1132 1132 if (err != 0) {
1133 goto fail;
1134 }
1133 zbc_val.depth = 0x1; 1135 zbc_val.depth = 0x1;
1134 zbc_val.format = ZBC_STENCIL_CLEAR_FMT_U8; 1136 zbc_val.format = ZBC_STENCIL_CLEAR_FMT_U8;
1135 err |= gr_gk20a_add_zbc(g, gr, &zbc_val); 1137 err = gr_gk20a_add_zbc(g, gr, &zbc_val);
1138 if (err != 0) {
1139 goto fail;
1140 }
1136 1141
1137 zbc_val.depth = 0xff; 1142 zbc_val.depth = 0xff;
1138 zbc_val.format = ZBC_STENCIL_CLEAR_FMT_U8; 1143 zbc_val.format = ZBC_STENCIL_CLEAR_FMT_U8;
1139 err |= gr_gk20a_add_zbc(g, gr, &zbc_val); 1144 err = gr_gk20a_add_zbc(g, gr, &zbc_val);
1140 1145 if (err != 0) {
1141 if (!err) { 1146 goto fail;
1142 gr->max_default_s_index = 3;
1143 } else {
1144 nvgpu_err(g, "fail to load default zbc stencil table");
1145 return err;
1146 } 1147 }
1147 1148
1149 gr->max_default_s_index = 3;
1150
1148 return 0; 1151 return 0;
1152
1153fail:
1154 nvgpu_err(g, "fail to load default zbc stencil table");
1155 return err;
1149} 1156}
1150 1157
1151int gr_gv11b_load_stencil_tbl(struct gk20a *g, struct gr_gk20a *gr) 1158int gr_gv11b_load_stencil_tbl(struct gk20a *g, struct gr_gk20a *gr)