diff options
author | Vinod G <vinodg@nvidia.com> | 2018-06-26 21:09:57 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-07-14 18:36:53 -0400 |
commit | ac98827c9d81746020dce689f9eb8c4018a8c148 (patch) | |
tree | 142dea7d1109be3b12a4e94c738a01ab7b13ee89 /drivers/gpu/nvgpu/gv11b | |
parent | b97bcb3c689426a1b099e88ceef4d55584e2362b (diff) |
gpu: nvgpu: Add L2 register read-backs following writes
LTC register write is followed by a register read
and if data doesn't match code will report the error.
Renamed existing nvgpu_writel_check function as
nvgpu_writel_loop as it loops until the write get success.
nvgpu_writel_check function write and read back and
compare the data.
Bug 2039150
Change-Id: I0a49be36aad23936f2d58aa82872710827da1d32
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1762344
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/ltc_gv11b.c | 21 |
1 files changed, 11 insertions, 10 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c index b64faaa6..48faa4d2 100644 --- a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c | |||
@@ -42,13 +42,12 @@ void gv11b_ltc_set_zbc_stencil_entry(struct gk20a *g, | |||
42 | { | 42 | { |
43 | u32 real_index = index + GK20A_STARTOF_ZBC_TABLE; | 43 | u32 real_index = index + GK20A_STARTOF_ZBC_TABLE; |
44 | 44 | ||
45 | gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_index_r(), | 45 | nvgpu_writel_check(g, ltc_ltcs_ltss_dstg_zbc_index_r(), |
46 | ltc_ltcs_ltss_dstg_zbc_index_address_f(real_index)); | 46 | ltc_ltcs_ltss_dstg_zbc_index_address_f(real_index)); |
47 | 47 | ||
48 | gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(), | 48 | nvgpu_writel_check(g, |
49 | stencil_val->depth); | 49 | ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(), |
50 | 50 | stencil_val->depth); | |
51 | gk20a_readl(g, ltc_ltcs_ltss_dstg_zbc_index_r()); | ||
52 | } | 51 | } |
53 | 52 | ||
54 | void gv11b_ltc_init_fs_state(struct gk20a *g) | 53 | void gv11b_ltc_init_fs_state(struct gk20a *g) |
@@ -72,13 +71,13 @@ void gv11b_ltc_init_fs_state(struct gk20a *g) | |||
72 | reg = gk20a_readl(g, ltc_ltcs_ltss_intr_r()); | 71 | reg = gk20a_readl(g, ltc_ltcs_ltss_intr_r()); |
73 | reg &= ~ltc_ltcs_ltss_intr_en_evicted_cb_m(); | 72 | reg &= ~ltc_ltcs_ltss_intr_en_evicted_cb_m(); |
74 | reg &= ~ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(); | 73 | reg &= ~ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(); |
75 | gk20a_writel(g, ltc_ltcs_ltss_intr_r(), reg); | 74 | nvgpu_writel_check(g, ltc_ltcs_ltss_intr_r(), reg); |
76 | 75 | ||
77 | /* Enable ECC interrupts */ | 76 | /* Enable ECC interrupts */ |
78 | ltc_intr = gk20a_readl(g, ltc_ltcs_ltss_intr_r()); | 77 | ltc_intr = gk20a_readl(g, ltc_ltcs_ltss_intr_r()); |
79 | ltc_intr |= ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f() | | 78 | ltc_intr |= ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f() | |
80 | ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(); | 79 | ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(); |
81 | gk20a_writel(g, ltc_ltcs_ltss_intr_r(), | 80 | nvgpu_writel_check(g, ltc_ltcs_ltss_intr_r(), |
82 | ltc_intr); | 81 | ltc_intr); |
83 | } | 82 | } |
84 | 83 | ||
@@ -133,14 +132,16 @@ void gv11b_ltc_isr(struct gk20a *g) | |||
133 | 132 | ||
134 | /* clear the interrupt */ | 133 | /* clear the interrupt */ |
135 | if ((corrected_delta > 0U) || corrected_overflow) { | 134 | if ((corrected_delta > 0U) || corrected_overflow) { |
136 | gk20a_writel(g, ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_r() + offset, 0); | 135 | nvgpu_writel_check(g, |
136 | ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_r() + offset, 0); | ||
137 | } | 137 | } |
138 | if ((uncorrected_delta > 0U) || uncorrected_overflow) { | 138 | if ((uncorrected_delta > 0U) || uncorrected_overflow) { |
139 | gk20a_writel(g, | 139 | nvgpu_writel_check(g, |
140 | ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_r() + offset, 0); | 140 | ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_r() + offset, 0); |
141 | } | 141 | } |
142 | 142 | ||
143 | gk20a_writel(g, ltc_ltc0_lts0_l2_cache_ecc_status_r() + offset, | 143 | nvgpu_writel_check(g, |
144 | ltc_ltc0_lts0_l2_cache_ecc_status_r() + offset, | ||
144 | ltc_ltc0_lts0_l2_cache_ecc_status_reset_task_f()); | 145 | ltc_ltc0_lts0_l2_cache_ecc_status_reset_task_f()); |
145 | 146 | ||
146 | /* update counters per slice */ | 147 | /* update counters per slice */ |