gpu: nvgpu: Add IOCTL for SM_EXCEPTION_TYPE_MASK

Add new ioctl to set the SM_EXCEPTION_TYPE_MASK is
added to dbg session.
Currently support SM_EXCEPTION_TYPE_MASK_FATAL type
If this type is set then the code will skip RC recovery,
instead trigger CILP preemption.

bug  200412641
JIRA NVGPU-702

Change-Id: I4b1f18379ee792cd324ccc555939e0f4f5c9e3b4
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1729792
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 18 insertions, 4 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index c925e5b6..9e36071f 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -2182,9 +2182,9 @@ static bool gr_gv11b_check_warp_esr_error(struct gk20a *g, u32 warp_esr_error)
 
         struct warp_esr_error_table_s warp_esr_error_table[] = {
                 { gr_gpc0_tpc0_sm0_hww_warp_esr_error_stack_error_f(),
-                        "STACK ERROR"},
+                                "STACK ERROR"},
                 { gr_gpc0_tpc0_sm0_hww_warp_esr_error_api_stack_error_f(),
-                        "API STACK ERROR"},
+                                "API STACK ERROR"},
                 { gr_gpc0_tpc0_sm0_hww_warp_esr_error_pc_wrap_f(),
                                 "PC WRAP ERROR"},
                 { gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_pc_f(),
@@ -2221,7 +2221,7 @@ static bool gr_gv11b_check_warp_esr_error(struct gk20a *g, u32 warp_esr_error)
                 if (warp_esr_error_table[index].error_value == warp_esr_error) {
                         esr_err = warp_esr_error_table[index].error_value;
                         nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg,
-                                "ESR %s(0x%x)",
+                                "WARP_ESR %s(0x%x)",
                                 warp_esr_error_table[index].error_name,
                                 esr_err);
                         break;
@@ -2250,6 +2250,21 @@ static int gr_gv11b_handle_all_warp_esr_errors(struct gk20a *g,
                 return 0;
         }
 
+        /*
+         * Check SET_EXCEPTION_TYPE_MASK is being set.
+         * If set, skip the recovery and trigger CILP
+         * If not set, trigger the recovery.
+         */
+        if ((g->gr.sm_exception_mask_type &
+                                        NVGPU_SM_EXCEPTION_TYPE_MASK_FATAL) ==
+                                        NVGPU_SM_EXCEPTION_TYPE_MASK_FATAL) {
+                nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg,
+                        "SM Exception Type Mask set %d,"
+                        "skip recovery",
+                        g->gr.sm_exception_mask_type);
+                return 0;
+        }
+
         if (fault_ch) {
                 tsg = &g->fifo.tsg[fault_ch->tsgid];
 
@@ -2294,7 +2309,6 @@ int gr_gv11b_pre_process_sm_exception(struct gk20a *g,
         u32 warp_esr_error = gr_gpc0_tpc0_sm0_hww_warp_esr_error_v(warp_esr);
         struct tsg_gk20a *tsg;
 
-
         *early_exit = false;
         *ignore_debugger = false;