gpu: nvgpu: Remove separation of t18x code

Remove separation of t18x specific code and fields and the associated
ifdefs. We can build T18x code in always.

Change-Id: I4e8eae9c30335632a2da48b418c6138193831b4f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1595431
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

3 files changed, 12 insertions, 10 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index 68ac8f51..9e43941d 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -280,7 +280,7 @@ static int gr_gv11b_handle_lrf_exception(struct gk20a *g, u32 gpc, u32 tpc,
                 lrf_corrected_err_count_delta +=
                         (is_lrf_ecc_corrected_total_err_overflow <<
                          gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_s());
-                g->ecc.gr.t18x.sm_lrf_single_err_count.counters[tpc] +=
+                g->ecc.gr.sm_lrf_single_err_count.counters[tpc] +=
                                                         lrf_corrected_err_count_delta;
                 gk20a_writel(g,
                         gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_r() + offset,
@@ -295,7 +295,7 @@ static int gr_gv11b_handle_lrf_exception(struct gk20a *g, u32 gpc, u32 tpc,
                 lrf_uncorrected_err_count_delta +=
                         (is_lrf_ecc_uncorrected_total_err_overflow <<
                          gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_s());
-                g->ecc.gr.t18x.sm_lrf_double_err_count.counters[tpc] +=
+                g->ecc.gr.sm_lrf_double_err_count.counters[tpc] +=
                                                         lrf_uncorrected_err_count_delta;
                 gk20a_writel(g,
                         gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_r() + offset,
@@ -1664,8 +1664,8 @@ void gr_gv11b_commit_global_attrib_cb(struct gk20a *g,
         struct gr_ctx_desc *gr_ctx = ch_ctx->gr_ctx;
         int attrBufferSize;
 
-        if (gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va)
-                attrBufferSize = gr_ctx->t18x.betacb_ctxsw_buffer.size;
+        if (gr_ctx->preempt_ctxsw_buffer.gpu_va)
+                attrBufferSize = gr_ctx->betacb_ctxsw_buffer.size;
         else
                 attrBufferSize = g->ops.gr.calc_global_ctx_buffer_size(g);
 
@@ -2385,10 +2385,10 @@ int gr_gv11b_init_fs_state(struct gk20a *g)
                          gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f());
         gk20a_writel(g, gr_gpcs_tpcs_sm_disp_ctrl_r(), data);
 
-        if (g->gr.t18x.fecs_feature_override_ecc_val != 0) {
+        if (g->gr.fecs_feature_override_ecc_val != 0) {
                 gk20a_writel(g,
                         gr_fecs_feature_override_ecc_r(),
-                        g->gr.t18x.fecs_feature_override_ecc_val);
+                        g->gr.fecs_feature_override_ecc_val);
         }
 
         return gr_gm20b_init_fs_state(g);
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
index b6ba231e..1941f239 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
@@ -46,6 +46,8 @@ struct zbc_query_params;
 struct channel_ctx_gk20a;
 struct nvgpu_warpstate;
 struct nvgpu_gr_sm_error_state;
+struct gr_gk20a_isr_data;
+struct gk20a_debug_output;
 
 enum {
         VOLTA_CHANNEL_GPFIFO_A  = 0xC36F,
diff --git a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c
index 95d82254..723e2e80 100644
--- a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c
+++ b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c
@@ -81,13 +81,13 @@ static int gv11b_tegra_probe(struct device *dev)
         platform->bypass_smmu = !device_is_iommuable(dev);
         platform->disable_bigpage = platform->bypass_smmu;
 
-        platform->g->gr.t18x.ctx_vars.dump_ctxsw_stats_on_channel_close
+        platform->g->gr.ctx_vars.dump_ctxsw_stats_on_channel_close
                 = false;
-        platform->g->gr.t18x.ctx_vars.dump_ctxsw_stats_on_channel_close
+        platform->g->gr.ctx_vars.dump_ctxsw_stats_on_channel_close
                 = false;
 
-        platform->g->gr.t18x.ctx_vars.force_preemption_gfxp = false;
-        platform->g->gr.t18x.ctx_vars.force_preemption_cilp = false;
+        platform->g->gr.ctx_vars.force_preemption_gfxp = false;
+        platform->g->gr.ctx_vars.force_preemption_cilp = false;
 
         gp10b_tegra_get_clocks(dev);
         nvgpu_linux_init_clk_support(platform->g);