gpu: nvgpu: Move ltc HAL to common

Move implementation of ltc HAL to common/ltc.

JIRA NVGPU-956

Change-Id: Id78d74e8612d7dacfb8d322d491abecd798e42b5
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1798461
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

4 files changed, 13 insertions, 253 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index c2cf909a..41d2f695 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -4716,11 +4716,11 @@ int gr_gv11b_decode_priv_addr(struct gk20a *g, u32 addr,
                 }
                 *be_num = pri_get_be_num(g, addr);
                 return 0;
-        } else if (pri_is_ltc_addr(addr)) {
+        } else if (g->ops.ltc.pri_is_ltc_addr(g, addr)) {
                 *addr_type = CTXSW_ADDR_TYPE_LTCS;
-                if (g->ops.gr.is_ltcs_ltss_addr(g, addr))
+                if (g->ops.ltc.is_ltcs_ltss_addr(g, addr))
                         *broadcast_flags |= PRI_BROADCAST_FLAGS_LTCS;
-                else if (g->ops.gr.is_ltcn_ltss_addr(g, addr))
+                else if (g->ops.ltc.is_ltcn_ltss_addr(g, addr))
                         *broadcast_flags |= PRI_BROADCAST_FLAGS_LTSS;
                 return 0;
         } else if (pri_is_fbpa_addr(g, addr)) {
@@ -4928,10 +4928,10 @@ int gr_gv11b_create_priv_addr_table(struct gk20a *g,
                 g->ops.gr.egpc_etpc_priv_addr_table(g, addr, gpc_num, tpc_num,
                                 broadcast_flags, priv_addr_table, &t);
         } else if (broadcast_flags & PRI_BROADCAST_FLAGS_LTSS) {
-                g->ops.gr.split_lts_broadcast_addr(g, addr,
+                g->ops.ltc.split_lts_broadcast_addr(g, addr,
                                                         priv_addr_table, &t);
         } else if (broadcast_flags & PRI_BROADCAST_FLAGS_LTCS) {
-                g->ops.gr.split_ltc_broadcast_addr(g, addr,
+                g->ops.ltc.split_ltc_broadcast_addr(g, addr,
                                                         priv_addr_table, &t);
         } else if (broadcast_flags & PRI_BROADCAST_FLAGS_FBPA) {
                 g->ops.gr.split_fbpa_broadcast_addr(g, addr,
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index 111a1ea2..3772649e 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -36,6 +36,9 @@
 #include "common/therm/therm_gm20b.h"
 #include "common/therm/therm_gp10b.h"
 #include "common/therm/therm_gv11b.h"
+#include "common/ltc/ltc_gm20b.h"
+#include "common/ltc/ltc_gp10b.h"
+#include "common/ltc/ltc_gv11b.h"
 
 #include "gk20a/gk20a.h"
 #include "gk20a/fifo_gk20a.h"
@@ -49,14 +52,12 @@
 #include "gk20a/pmu_gk20a.h"
 #include "gk20a/gr_gk20a.h"
 
-#include "gm20b/ltc_gm20b.h"
 #include "gm20b/gr_gm20b.h"
 #include "gm20b/fifo_gm20b.h"
 #include "gm20b/mm_gm20b.h"
 #include "gm20b/acr_gm20b.h"
 #include "gm20b/pmu_gm20b.h"
 
-#include "gp10b/ltc_gp10b.h"
 #include "gp10b/mc_gp10b.h"
 #include "gp10b/ce_gp10b.h"
 #include "gp10b/fifo_gp10b.h"
@@ -76,7 +77,6 @@
 #include "css_gr_gv11b.h"
 #include "gr_gv11b.h"
 #include "mc_gv11b.h"
-#include "ltc_gv11b.h"
 #include "gv11b.h"
 #include "ce_gv11b.h"
 #include "gr_ctx_gv11b.h"
@@ -245,6 +245,11 @@ static const struct gpu_ops gv11b_ops = {
                 .flush = gm20b_flush_ltc,
                 .set_enabled = gp10b_ltc_set_enabled,
                 .intr_en_illegal_compstat = gv11b_ltc_intr_en_illegal_compstat,
+                .pri_is_ltc_addr = gm20b_ltc_pri_is_ltc_addr,
+                .is_ltcs_ltss_addr = gm20b_ltc_is_ltcs_ltss_addr,
+                .is_ltcn_ltss_addr = gm20b_ltc_is_ltcn_ltss_addr,
+                .split_lts_broadcast_addr = gm20b_ltc_split_lts_broadcast_addr,
+                .split_ltc_broadcast_addr = gm20b_ltc_split_ltc_broadcast_addr,
         },
         .ce2 = {
                 .isr_stall = gv11b_ce_isr,
@@ -332,10 +337,6 @@ static const struct gpu_ops gv11b_ops = {
                 .init_sm_id_table = gr_gv100_init_sm_id_table,
                 .load_smid_config = gr_gv11b_load_smid_config,
                 .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering,
-                .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr,
-                .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr,
-                .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr,
-                .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr,
                 .setup_rop_mapping = gr_gv11b_setup_rop_mapping,
                 .program_zcull_mapping = gr_gv11b_program_zcull_mapping,
                 .commit_global_timeslice = gr_gv11b_commit_global_timeslice,
diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c
deleted file mode 100644
index d7c385a9..00000000
--- a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c
+++ /dev/null
@@ -1,207 +0,0 @@
-/*
- * GV11B LTC
- *
- * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#include <nvgpu/io.h>
-#include "gk20a/gk20a.h"
-#include "gp10b/ltc_gp10b.h"
-
-#include "ltc_gv11b.h"
-
-#include <nvgpu/hw/gv11b/hw_ltc_gv11b.h>
-#include <nvgpu/hw/gv11b/hw_mc_gv11b.h>
-#include <nvgpu/hw/gv11b/hw_top_gv11b.h>
-#include <nvgpu/hw/gv11b/hw_mc_gv11b.h>
-
-#include <nvgpu/utils.h>
-
-/*
- * Sets the ZBC stencil for the passed index.
- */
-void gv11b_ltc_set_zbc_stencil_entry(struct gk20a *g,
-                                          struct zbc_entry *stencil_val,
-                                          u32 index)
-{
-        u32 real_index = index + GK20A_STARTOF_ZBC_TABLE;
-
-        nvgpu_writel_check(g, ltc_ltcs_ltss_dstg_zbc_index_r(),
-                     ltc_ltcs_ltss_dstg_zbc_index_address_f(real_index));
-
-        nvgpu_writel_check(g,
-                           ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(),
-                           stencil_val->depth);
-}
-
-void gv11b_ltc_init_fs_state(struct gk20a *g)
-{
-        struct gr_gk20a *gr = &g->gr;
-        u32 ltc_intr;
-        u32 reg;
-
-        nvgpu_log_info(g, "initialize gv11b l2");
-
-        g->max_ltc_count = gk20a_readl(g, top_num_ltcs_r());
-        g->ltc_count = g->ops.priv_ring.enum_ltc(g);
-        nvgpu_log_info(g, "%u ltcs out of %u", g->ltc_count, g->max_ltc_count);
-
-        reg = gk20a_readl(g, ltc_ltcs_ltss_cbc_param_r());
-        gr->slices_per_ltc = ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(reg);;
-        gr->cacheline_size =
-                512U << ltc_ltcs_ltss_cbc_param_cache_line_size_v(reg);
-
-        /* Disable LTC interrupts */
-        reg = gk20a_readl(g, ltc_ltcs_ltss_intr_r());
-        reg &= ~ltc_ltcs_ltss_intr_en_evicted_cb_m();
-        reg &= ~ltc_ltcs_ltss_intr_en_illegal_compstat_access_m();
-        nvgpu_writel_check(g, ltc_ltcs_ltss_intr_r(), reg);
-
-        if (g->ops.ltc.intr_en_illegal_compstat)
-                g->ops.ltc.intr_en_illegal_compstat(g,
-                                        g->ltc_intr_en_illegal_compstat);
-
-        /* Enable ECC interrupts */
-        ltc_intr = gk20a_readl(g, ltc_ltcs_ltss_intr_r());
-        ltc_intr |= ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f() |
-                ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f();
-        nvgpu_writel_check(g, ltc_ltcs_ltss_intr_r(),
-                                ltc_intr);
-}
-
-void gv11b_ltc_intr_en_illegal_compstat(struct gk20a *g, bool enable)
-{
-        u32 val;
-
-        /* disble/enble illegal_compstat interrupt */
-        val = gk20a_readl(g, ltc_ltcs_ltss_intr_r());
-        if (enable)
-                val = set_field(val,
-                        ltc_ltcs_ltss_intr_en_illegal_compstat_m(),
-                        ltc_ltcs_ltss_intr_en_illegal_compstat_enabled_f());
-        else
-                val = set_field(val,
-                        ltc_ltcs_ltss_intr_en_illegal_compstat_m(),
-                        ltc_ltcs_ltss_intr_en_illegal_compstat_disabled_f());
-        gk20a_writel(g, ltc_ltcs_ltss_intr_r(), val);
-}
-
-
-void gv11b_ltc_isr(struct gk20a *g)
-{
-        u32 mc_intr, ltc_intr3;
-        unsigned int ltc, slice;
-        u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE);
-        u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE);
-        u32 ecc_status, ecc_addr, corrected_cnt, uncorrected_cnt;
-        u32 corrected_delta, uncorrected_delta;
-        u32 corrected_overflow, uncorrected_overflow;
-
-        mc_intr = gk20a_readl(g, mc_intr_ltc_r());
-        for (ltc = 0; ltc < g->ltc_count; ltc++) {
-                if ((mc_intr & 1U << ltc) == 0)
-                        continue;
-
-                for (slice = 0; slice < g->gr.slices_per_ltc; slice++) {
-                        u32 offset = ltc_stride * ltc + lts_stride * slice;
-                        ltc_intr3 = gk20a_readl(g, ltc_ltc0_lts0_intr3_r() +
-                                                offset);
-
-                        /* Detect and handle ECC PARITY errors */
-
-                        if (ltc_intr3 &
-                                (ltc_ltcs_ltss_intr3_ecc_uncorrected_m() |
-                                 ltc_ltcs_ltss_intr3_ecc_corrected_m())) {
-
-                                ecc_status = gk20a_readl(g,
-                                        ltc_ltc0_lts0_l2_cache_ecc_status_r() +
-                                        offset);
-                                ecc_addr = gk20a_readl(g,
-                                        ltc_ltc0_lts0_l2_cache_ecc_address_r() +
-                                        offset);
-                                corrected_cnt = gk20a_readl(g,
-                                        ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_r() + offset);
-                                uncorrected_cnt = gk20a_readl(g,
-                                        ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_r() + offset);
-
-                                corrected_delta =
-                                        ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_v(corrected_cnt);
-                                uncorrected_delta =
-                                        ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_v(uncorrected_cnt);
-                                corrected_overflow = ecc_status &
-                                        ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_total_counter_overflow_m();
-
-                                uncorrected_overflow = ecc_status &
-                                        ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_total_counter_overflow_m();
-
-                                /* clear the interrupt */
-                                if ((corrected_delta > 0U) || corrected_overflow) {
-                                        nvgpu_writel_check(g,
-                                                ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_r() + offset, 0);
-                                }
-                                if ((uncorrected_delta > 0U) || uncorrected_overflow) {
-                                        nvgpu_writel_check(g,
-                                                ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_r() + offset, 0);
-                                }
-
-                                nvgpu_writel_check(g,
-                                        ltc_ltc0_lts0_l2_cache_ecc_status_r() + offset,
-                                        ltc_ltc0_lts0_l2_cache_ecc_status_reset_task_f());
-
-                                /* update counters per slice */
-                                if (corrected_overflow)
-                                        corrected_delta += (0x1U << ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_s());
-                                if (uncorrected_overflow)
-                                        uncorrected_delta += (0x1U << ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_s());
-
-                                g->ecc.ltc.ecc_sec_count[ltc][slice].counter += corrected_delta;
-                                g->ecc.ltc.ecc_ded_count[ltc][slice].counter += uncorrected_delta;
-                                nvgpu_log(g, gpu_dbg_intr,
-                                        "ltc:%d lts: %d cache ecc interrupt intr: 0x%x", ltc, slice, ltc_intr3);
-
-                                if (ecc_status & ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_rstg_m())
-                                        nvgpu_log(g, gpu_dbg_intr, "rstg ecc error corrected");
-                                if (ecc_status & ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_rstg_m())
-                                        nvgpu_log(g, gpu_dbg_intr, "rstg ecc error uncorrected");
-                                if (ecc_status & ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_tstg_m())
-                                        nvgpu_log(g, gpu_dbg_intr, "tstg ecc error corrected");
-                                if (ecc_status & ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_tstg_m())
-                                        nvgpu_log(g, gpu_dbg_intr, "tstg ecc error uncorrected");
-                                if (ecc_status & ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_dstg_m())
-                                        nvgpu_log(g, gpu_dbg_intr, "dstg ecc error corrected");
-                                if (ecc_status & ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_dstg_m())
-                                        nvgpu_log(g, gpu_dbg_intr, "dstg ecc error uncorrected");
-
-                                if (corrected_overflow || uncorrected_overflow)
-                                        nvgpu_info(g, "ecc counter overflow!");
-
-                                nvgpu_log(g, gpu_dbg_intr,
-                                        "ecc error address: 0x%x", ecc_addr);
-
-                        }
-
-                }
-
-        }
-
-        /* fallback to other interrupts  */
-        gp10b_ltc_isr(g);
-}
diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.h b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.h
deleted file mode 100644
index 9d33b9fb..00000000
--- a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef LTC_GV11B_H
-#define LTC_GV11B_H
-struct gk20a;
-
-void gv11b_ltc_set_zbc_stencil_entry(struct gk20a *g,
-                                          struct zbc_entry *stencil_val,
-                                          u32 index);
-void gv11b_ltc_init_fs_state(struct gk20a *g);
-void gv11b_ltc_intr_en_illegal_compstat(struct gk20a *g, bool enable);
-void gv11b_ltc_isr(struct gk20a *g);
-
-#endif