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authorMahantesh Kumbar <mkumbar@nvidia.com>2018-09-10 11:41:49 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-09-24 11:12:03 -0400
commit863b47064445b3dd5cdc354821c8d3d14deade33 (patch)
tree1e53f26c1549d1970d752f74ab82a4d55642620b /drivers/gpu/nvgpu/gv11b
parentfdf77eda18b59c305d4dd8436d8b09d42ec4718a (diff)
gpu: nvgpu: PMU init sequence change
-Moved PMU RTOS init & start RTOS from acr_gm20b.c file pmu.c method nvgpu_init_pmu_support() -Modified nvgpu_init_pmu_support() to init required interface for PMU RTOS & does start PMU RTOS in secure & non-secure based on NVGPU_SEC_PRIVSECURITY flag. -Created secured_pmu_start ops under PMU ops to start PMU falcon in low secure mode. -Updated PMU ops update_lspmu_cmdline_args, setup_apertures & secured_pmu_start assignment for gp106 & gv100 to support modified PMU init sequence. -Removed duplicate PMU non-secure bootstrap code from multiple files & defined gm20b_ns_pmu_setup_hw_and_bootstrap()method to handle non secure PMU bootstrap, reused this method for need chips. JIRA NVGPU-1146 Change-Id: I3957da2936b3c4ea0c985e67802c847c38de7c89 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1818099 Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b')
-rw-r--r--drivers/gpu/nvgpu/gv11b/hal_gv11b.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index 18b00ea4..665e2ed1 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -888,6 +888,7 @@ int gv11b_init_hal(struct gk20a *g)
888 gops->pmu.update_lspmu_cmdline_args = 888 gops->pmu.update_lspmu_cmdline_args =
889 gm20b_update_lspmu_cmdline_args; 889 gm20b_update_lspmu_cmdline_args;
890 gops->pmu.setup_apertures = gv11b_setup_apertures; 890 gops->pmu.setup_apertures = gv11b_setup_apertures;
891 gops->pmu.secured_pmu_start = gm20b_secured_pmu_start;
891 892
892 gops->pmu.init_wpr_region = gm20b_pmu_init_acr; 893 gops->pmu.init_wpr_region = gm20b_pmu_init_acr;
893 gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; 894 gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode;
@@ -898,6 +899,8 @@ int gv11b_init_hal(struct gk20a *g)
898 } else { 899 } else {
899 /* Inherit from gk20a */ 900 /* Inherit from gk20a */
900 gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob, 901 gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob,
902 gops->pmu.pmu_setup_hw_and_bootstrap =
903 gm20b_ns_pmu_setup_hw_and_bootstrap;
901 904
902 gops->pmu.load_lsfalcon_ucode = NULL; 905 gops->pmu.load_lsfalcon_ucode = NULL;
903 gops->pmu.init_wpr_region = NULL; 906 gops->pmu.init_wpr_region = NULL;