diff options
author | Philemon Gardet <pgardet@nvidia.com> | 2018-07-20 23:37:54 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-08-22 20:30:15 -0400 |
commit | 650171566bff59e9eb372f213fdce4dfbb6da5bd (patch) | |
tree | f7125ce134cdb79ab0e35d70330ea79c8b11af2f /drivers/gpu/nvgpu/gv11b | |
parent | 138e70b0d40609b896ab576a8f0ea23e23c7825b (diff) |
gpu: nvgpu: gv100: Fix nonpes aware tpc mapping
For gv1xx, kernel smid configuration programming is done based
on nonpes aware tpc. On gv100 the registers GPM_PD_SM_ID and SM_CFG
are indexed on nonpes aware tpc.
Bug 2096878
Change-Id: I0edc2f066e2c3b35057fde102689a9f1915c72ea
Signed-off-by: Philemon Gardet <pgardet@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1783046
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Sandarbh Jain <sanjain@nvidia.com>
Tested-by: Sandarbh Jain <sanjain@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 5d237839..ee736d15 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -2746,13 +2746,14 @@ void gr_gv11b_program_sm_id_numbering(struct gk20a *g, | |||
2746 | u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, | 2746 | u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, |
2747 | GPU_LIT_TPC_IN_GPC_STRIDE); | 2747 | GPU_LIT_TPC_IN_GPC_STRIDE); |
2748 | u32 gpc_offset = gpc_stride * gpc; | 2748 | u32 gpc_offset = gpc_stride * gpc; |
2749 | u32 tpc_offset = tpc_in_gpc_stride * tpc; | ||
2750 | u32 global_tpc_index = g->gr.sm_to_cluster[smid].global_tpc_index; | 2749 | u32 global_tpc_index = g->gr.sm_to_cluster[smid].global_tpc_index; |
2750 | u32 tpc_offset; | ||
2751 | 2751 | ||
2752 | tpc = g->ops.gr.get_nonpes_aware_tpc(g, gpc, tpc); | 2752 | tpc = g->ops.gr.get_nonpes_aware_tpc(g, gpc, tpc); |
2753 | tpc_offset = tpc_in_gpc_stride * tpc; | ||
2753 | 2754 | ||
2754 | gk20a_writel(g, gr_gpc0_tpc0_sm_cfg_r() + gpc_offset + tpc_offset, | 2755 | gk20a_writel(g, gr_gpc0_tpc0_sm_cfg_r() + gpc_offset + tpc_offset, |
2755 | gr_gpc0_tpc0_sm_cfg_tpc_id_f(global_tpc_index)); | 2756 | gr_gpc0_tpc0_sm_cfg_tpc_id_f(global_tpc_index)); |
2756 | gk20a_writel(g, gr_gpc0_gpm_pd_sm_id_r(tpc) + gpc_offset, | 2757 | gk20a_writel(g, gr_gpc0_gpm_pd_sm_id_r(tpc) + gpc_offset, |
2757 | gr_gpc0_gpm_pd_sm_id_id_f(global_tpc_index)); | 2758 | gr_gpc0_gpm_pd_sm_id_id_f(global_tpc_index)); |
2758 | gk20a_writel(g, gr_gpc0_tpc0_pe_cfg_smid_r() + gpc_offset + tpc_offset, | 2759 | gk20a_writel(g, gr_gpc0_tpc0_pe_cfg_smid_r() + gpc_offset + tpc_offset, |