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authorKonsta Holtta <kholtta@nvidia.com>2018-08-27 07:16:59 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-08-31 00:42:39 -0400
commit5e90bf3f6c35361cacc1ce8588c3120091d54f58 (patch)
tree28155f352d97f33adff9fa62f06cb87d1570925b /drivers/gpu/nvgpu/gv11b
parenta6108a4b0ed52c7a8fa58d9815d0b373be8305bf (diff)
gpu: nvgpu: remove ctx header desc type
The graphics subctx header object is nothing but memory. Drop the dependency to gr header file in the channel header file and substitute struct nvgpu_mem for struct ctx_header_desc. Jira NVGPU-967 Change-Id: Ic3976391016c42d2ada4aac3e0851a1222244ce9 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1807370 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b')
-rw-r--r--drivers/gpu/nvgpu/gv11b/gr_gv11b.c11
-rw-r--r--drivers/gpu/nvgpu/gv11b/subctx_gv11b.c48
2 files changed, 28 insertions, 31 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index 296d8e90..9a6afa3e 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -1682,8 +1682,7 @@ void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g,
1682{ 1682{
1683 struct tsg_gk20a *tsg; 1683 struct tsg_gk20a *tsg;
1684 struct nvgpu_gr_ctx *gr_ctx; 1684 struct nvgpu_gr_ctx *gr_ctx;
1685 struct ctx_header_desc *ctx = &c->ctx_header; 1685 struct nvgpu_mem *ctxheader = &c->ctx_header;
1686 struct nvgpu_mem *ctxheader = &ctx->mem;
1687 u32 gfxp_preempt_option = 1686 u32 gfxp_preempt_option =
1688 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(); 1687 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f();
1689 u32 cilp_preempt_option = 1688 u32 cilp_preempt_option =
@@ -2897,7 +2896,7 @@ int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va)
2897{ 2896{
2898 u32 addr_lo; 2897 u32 addr_lo;
2899 u32 addr_hi; 2898 u32 addr_hi;
2900 struct ctx_header_desc *ctx; 2899 struct nvgpu_mem *ctxheader;
2901 int err; 2900 int err;
2902 struct gk20a *g = c->g; 2901 struct gk20a *g = c->g;
2903 2902
@@ -2913,9 +2912,9 @@ int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va)
2913 return err; 2912 return err;
2914 } 2913 }
2915 2914
2916 ctx = &c->ctx_header; 2915 ctxheader = &c->ctx_header;
2917 addr_lo = u64_lo32(ctx->mem.gpu_va) >> ram_in_base_shift_v(); 2916 addr_lo = u64_lo32(ctxheader->gpu_va) >> ram_in_base_shift_v();
2918 addr_hi = u64_hi32(ctx->mem.gpu_va); 2917 addr_hi = u64_hi32(ctxheader->gpu_va);
2919 2918
2920 /* point this address to engine_wfi_ptr */ 2919 /* point this address to engine_wfi_ptr */
2921 nvgpu_mem_wr32(c->g, &c->inst_block, ram_in_engine_wfi_target_w(), 2920 nvgpu_mem_wr32(c->g, &c->inst_block, ram_in_engine_wfi_target_w(),
diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c
index d742e8dc..4e429567 100644
--- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c
@@ -43,42 +43,42 @@ static void gv11b_subctx_commit_pdb(struct vm_gk20a *vm,
43 43
44void gv11b_free_subctx_header(struct channel_gk20a *c) 44void gv11b_free_subctx_header(struct channel_gk20a *c)
45{ 45{
46 struct ctx_header_desc *ctx = &c->ctx_header; 46 struct nvgpu_mem *ctxheader = &c->ctx_header;
47 struct gk20a *g = c->g; 47 struct gk20a *g = c->g;
48 48
49 nvgpu_log(g, gpu_dbg_fn, "gv11b_free_subctx_header"); 49 nvgpu_log(g, gpu_dbg_fn, "gv11b_free_subctx_header");
50 50
51 if (ctx->mem.gpu_va) { 51 if (ctxheader->gpu_va) {
52 nvgpu_gmmu_unmap(c->vm, &ctx->mem, ctx->mem.gpu_va); 52 nvgpu_gmmu_unmap(c->vm, ctxheader, ctxheader->gpu_va);
53 53
54 nvgpu_dma_free(g, &ctx->mem); 54 nvgpu_dma_free(g, ctxheader);
55 } 55 }
56} 56}
57 57
58int gv11b_alloc_subctx_header(struct channel_gk20a *c) 58int gv11b_alloc_subctx_header(struct channel_gk20a *c)
59{ 59{
60 struct ctx_header_desc *ctx = &c->ctx_header; 60 struct nvgpu_mem *ctxheader = &c->ctx_header;
61 struct gk20a *g = c->g; 61 struct gk20a *g = c->g;
62 int ret = 0; 62 int ret = 0;
63 63
64 nvgpu_log(g, gpu_dbg_fn, "gv11b_alloc_subctx_header"); 64 nvgpu_log(g, gpu_dbg_fn, "gv11b_alloc_subctx_header");
65 65
66 if (!nvgpu_mem_is_valid(&ctx->mem)) { 66 if (!nvgpu_mem_is_valid(ctxheader)) {
67 ret = nvgpu_dma_alloc_sys(g, ctxsw_prog_fecs_header_v(), 67 ret = nvgpu_dma_alloc_sys(g, ctxsw_prog_fecs_header_v(),
68 &ctx->mem); 68 ctxheader);
69 if (ret) { 69 if (ret) {
70 nvgpu_err(g, "failed to allocate sub ctx header"); 70 nvgpu_err(g, "failed to allocate sub ctx header");
71 return ret; 71 return ret;
72 } 72 }
73 ctx->mem.gpu_va = nvgpu_gmmu_map(c->vm, 73 ctxheader->gpu_va = nvgpu_gmmu_map(c->vm,
74 &ctx->mem, 74 ctxheader,
75 ctx->mem.size, 75 ctxheader->size,
76 0, /* not GPU-cacheable */ 76 0, /* not GPU-cacheable */
77 gk20a_mem_flag_none, true, 77 gk20a_mem_flag_none, true,
78 ctx->mem.aperture); 78 ctxheader->aperture);
79 if (!ctx->mem.gpu_va) { 79 if (!ctxheader->gpu_va) {
80 nvgpu_err(g, "failed to map ctx header"); 80 nvgpu_err(g, "failed to map ctx header");
81 nvgpu_dma_free(g, &ctx->mem); 81 nvgpu_dma_free(g, ctxheader);
82 return -ENOMEM; 82 return -ENOMEM;
83 } 83 }
84 } 84 }
@@ -96,8 +96,7 @@ void gv11b_init_subcontext_pdb(struct vm_gk20a *vm,
96 96
97int gv11b_update_subctx_header(struct channel_gk20a *c, u64 gpu_va) 97int gv11b_update_subctx_header(struct channel_gk20a *c, u64 gpu_va)
98{ 98{
99 struct ctx_header_desc *ctx = &c->ctx_header; 99 struct nvgpu_mem *ctxheader = &c->ctx_header;
100 struct nvgpu_mem *gr_mem;
101 struct gk20a *g = c->g; 100 struct gk20a *g = c->g;
102 int ret = 0; 101 int ret = 0;
103 u32 addr_lo, addr_hi; 102 u32 addr_lo, addr_hi;
@@ -111,40 +110,39 @@ int gv11b_update_subctx_header(struct channel_gk20a *c, u64 gpu_va)
111 110
112 gr_ctx = &tsg->gr_ctx; 111 gr_ctx = &tsg->gr_ctx;
113 112
114 gr_mem = &ctx->mem;
115 g->ops.mm.l2_flush(g, true); 113 g->ops.mm.l2_flush(g, true);
116 114
117 /* set priv access map */ 115 /* set priv access map */
118 addr_lo = u64_lo32(gr_ctx->global_ctx_buffer_va[PRIV_ACCESS_MAP_VA]); 116 addr_lo = u64_lo32(gr_ctx->global_ctx_buffer_va[PRIV_ACCESS_MAP_VA]);
119 addr_hi = u64_hi32(gr_ctx->global_ctx_buffer_va[PRIV_ACCESS_MAP_VA]); 117 addr_hi = u64_hi32(gr_ctx->global_ctx_buffer_va[PRIV_ACCESS_MAP_VA]);
120 nvgpu_mem_wr(g, gr_mem, 118 nvgpu_mem_wr(g, ctxheader,
121 ctxsw_prog_main_image_priv_access_map_addr_lo_o(), 119 ctxsw_prog_main_image_priv_access_map_addr_lo_o(),
122 addr_lo); 120 addr_lo);
123 nvgpu_mem_wr(g, gr_mem, 121 nvgpu_mem_wr(g, ctxheader,
124 ctxsw_prog_main_image_priv_access_map_addr_hi_o(), 122 ctxsw_prog_main_image_priv_access_map_addr_hi_o(),
125 addr_hi); 123 addr_hi);
126 124
127 addr_lo = u64_lo32(gr_ctx->patch_ctx.mem.gpu_va); 125 addr_lo = u64_lo32(gr_ctx->patch_ctx.mem.gpu_va);
128 addr_hi = u64_hi32(gr_ctx->patch_ctx.mem.gpu_va); 126 addr_hi = u64_hi32(gr_ctx->patch_ctx.mem.gpu_va);
129 nvgpu_mem_wr(g, gr_mem, 127 nvgpu_mem_wr(g, ctxheader,
130 ctxsw_prog_main_image_patch_adr_lo_o(), 128 ctxsw_prog_main_image_patch_adr_lo_o(),
131 addr_lo); 129 addr_lo);
132 nvgpu_mem_wr(g, gr_mem, 130 nvgpu_mem_wr(g, ctxheader,
133 ctxsw_prog_main_image_patch_adr_hi_o(), 131 ctxsw_prog_main_image_patch_adr_hi_o(),
134 addr_hi); 132 addr_hi);
135 133
136 g->ops.gr.write_pm_ptr(g, gr_mem, gr_ctx->pm_ctx.mem.gpu_va); 134 g->ops.gr.write_pm_ptr(g, ctxheader, gr_ctx->pm_ctx.mem.gpu_va);
137 g->ops.gr.write_zcull_ptr(g, gr_mem, gr_ctx->zcull_ctx.gpu_va); 135 g->ops.gr.write_zcull_ptr(g, ctxheader, gr_ctx->zcull_ctx.gpu_va);
138 136
139 addr_lo = u64_lo32(gpu_va); 137 addr_lo = u64_lo32(gpu_va);
140 addr_hi = u64_hi32(gpu_va); 138 addr_hi = u64_hi32(gpu_va);
141 139
142 nvgpu_mem_wr(g, gr_mem, 140 nvgpu_mem_wr(g, ctxheader,
143 ctxsw_prog_main_image_context_buffer_ptr_hi_o(), addr_hi); 141 ctxsw_prog_main_image_context_buffer_ptr_hi_o(), addr_hi);
144 nvgpu_mem_wr(g, gr_mem, 142 nvgpu_mem_wr(g, ctxheader,
145 ctxsw_prog_main_image_context_buffer_ptr_o(), addr_lo); 143 ctxsw_prog_main_image_context_buffer_ptr_o(), addr_lo);
146 144
147 nvgpu_mem_wr(g, gr_mem, 145 nvgpu_mem_wr(g, ctxheader,
148 ctxsw_prog_main_image_ctl_o(), 146 ctxsw_prog_main_image_ctl_o(),
149 ctxsw_prog_main_image_ctl_type_per_veid_header_v()); 147 ctxsw_prog_main_image_ctl_type_per_veid_header_v());
150 148