gpu: nvgpu: gv11b: Use secure PMU reset for GV11B.

PMU reset for GV11B is PRIV protected.
gp106_pmu_reset() also uses the same register
to reset PMU, therefore used same function for
gv11b.

Change-Id: I633a96256598e73ed02cbdfe0afdb9fba8b76afd
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: http://git-master/r/1303740
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>

1 files changed, 2 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c
index 8432bd20..29ef7f6c 100644
--- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c
@@ -21,6 +21,7 @@
 #include "gk20a/gk20a.h"
 
 #include "gp10b/pmu_gp10b.h"
+#include "gp106/pmu_gp106.h"
 
 #include "pmu_gv11b.h"
 
@@ -153,6 +154,7 @@ void gv11b_init_pmu_ops(struct gpu_ops *gops)
         gp10b_init_pmu_ops(gops);
         gops->pmu.pmu_nsbootstrap = gv11b_pmu_bootstrap;
         gops->pmu.is_pmu_supported = gv11b_is_pmu_supported;
+        gops->pmu.reset = gp106_pmu_reset;
         gops->pmu.pmu_get_queue_head = pwr_pmu_queue_head_r;
         gops->pmu.pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v;
         gops->pmu.pmu_get_queue_tail = pwr_pmu_queue_tail_r;