gpu: nvgpu: add igpu support for clk_arbiter.

This patch constructs clk_arbiter specific code for gp10b as well as
gv11b and does the necessary plumbing in the clk_arbiter code. The
changes made are as follows.

1) Constructed clk_arb_gp10b.* files which add support for clk_arb
related HALS including the nvgpu_clk_arb_init and nvgpu_clk_arb_cb.
This doesn't have support for debugfs nor the VFUpdateEvent yet and
consequently no support for arb->notifications.

2) Added gpcclk specific variables corresponding to every gpc2clk in
a given clk_arb related struct.

3) Linux specific support_clk_freq_controller is assigned true in
platform_gp10b.c and platform_gv11b.c files.

4) Incremented the clk_arb_worker.put atomic variable during
worker_deinit so as to allow the worker thread to be stopped.

5) Added the flag clk_arb_events_supported as part of struct
nvgpu_clk_arb. This flag is used to selectively account for the extra
refcounting present in OS specific code i.e.
nvgpu_clk_arb_commit_request_fd. For igpus, the extra refcount is
reduced during nvgpu_clk_arb_release_completion_dev.

Bug 2061372

Change-Id: Id00acb106db2b46e55aa0324034a16a73723c078
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1774281
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 11 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index 591a7786..9444002b 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -67,6 +67,7 @@
 #include "gp10b/mm_gp10b.h"
 #include "gp10b/pmu_gp10b.h"
 #include "gp10b/gr_gp10b.h"
+#include "gp10b/clk_arb_gp10b.h"
 
 #include "gp106/pmu_gp106.h"
 #include "gp106/acr_gp106.h"
@@ -708,6 +709,15 @@ static const struct gpu_ops gv11b_ops = {
                 .handle_ext_irq = gv11b_pmu_handle_ext_irq,
                 .is_debug_mode_enabled = gm20b_pmu_is_debug_mode_en,
         },
+        .clk_arb = {
+                .get_arbiter_clk_domains = gp10b_get_arbiter_clk_domains,
+                .get_arbiter_f_points = gp10b_get_arbiter_f_points,
+                .get_arbiter_clk_range = gp10b_get_arbiter_clk_range,
+                .get_arbiter_clk_default = gp10b_get_arbiter_clk_default,
+                .arbiter_clk_init = gp10b_init_clk_arbiter,
+                .clk_arb_run_arbiter_cb = gp10b_clk_arb_run_arbiter_cb,
+                .clk_arb_cleanup = gp10b_clk_arb_cleanup,
+        },
         .regops = {
                 .exec_regops = exec_regops_gk20a,
                 .get_global_whitelist_ranges =
@@ -847,6 +857,7 @@ int gv11b_init_hal(struct gk20a *g)
         gops->falcon = gv11b_ops.falcon;
         gops->priv_ring = gv11b_ops.priv_ring;
         gops->fuse = gv11b_ops.fuse;
+        gops->clk_arb = gv11b_ops.clk_arb;
 
         /* Lone functions */
         gops->chip_init_gpu_characteristics =