gpu: nvgpu: gv11b: handle l2 related changes

Implemented gv11b specific l2 state init and Configured
ltc_ltcs_ltss_cbc_num_active_ltcs_r with following info:

- cbc_num_active_ltcs is read only for gv11b, so did not
  write any data to that field.
- enforced serilized access to l2 from sysmem and peermem.
- nvlink connected peer trafic sent through l2

JIRA GV11B-71

Change-Id: I63d9ee3f0a6da62e672a34e207f1f5214b6ed1b4
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1312831
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 38 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c
index 85ff33d2..70919f24 100644
--- a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c
@@ -20,6 +20,8 @@
 #include "ltc_gv11b.h"
 
 #include <nvgpu/hw/gv11b/hw_ltc_gv11b.h>
+#include <nvgpu/hw/gv11b/hw_top_gv11b.h>
+#include <nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h>
 
 /*
  * Sets the ZBC stencil for the passed index.
@@ -39,8 +41,44 @@ static void gv11b_ltc_set_zbc_stencil_entry(struct gk20a *g,
         gk20a_readl(g, ltc_ltcs_ltss_dstg_zbc_index_r());
 }
 
+static void gv11b_ltc_init_fs_state(struct gk20a *g)
+{
+        u32 ltc_intr;
+        u32 reg;
+
+        gk20a_dbg_info("initialize gv11b l2");
+
+        g->max_ltc_count = gk20a_readl(g, top_num_ltcs_r());
+        g->ltc_count = gk20a_readl(g, pri_ringmaster_enum_ltc_r());
+        gk20a_dbg_info("%u ltcs out of %u", g->ltc_count, g->max_ltc_count);
+
+        reg = gk20a_readl(g, ltc_ltcs_ltss_cbc_num_active_ltcs_r());
+        reg |= ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_f(true)
+                | ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_f(true);
+        gk20a_writel(g, ltc_ltcs_ltss_cbc_num_active_ltcs_r(), reg);
+
+        gk20a_writel(g, ltc_ltcs_ltss_dstg_cfg0_r(),
+                gk20a_readl(g, ltc_ltc0_lts0_dstg_cfg0_r()) |
+                ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m());
+
+        /* Disable LTC interrupts */
+        reg = gk20a_readl(g, ltc_ltcs_ltss_intr_r());
+        reg &= ~ltc_ltcs_ltss_intr_en_evicted_cb_m();
+        reg &= ~ltc_ltcs_ltss_intr_en_illegal_compstat_access_m();
+        gk20a_writel(g, ltc_ltcs_ltss_intr_r(), reg);
+
+        /* Enable ECC interrupts */
+        ltc_intr = gk20a_readl(g, ltc_ltcs_ltss_intr_r());
+        ltc_intr |= ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f() |
+                ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f();
+        gk20a_writel(g, ltc_ltcs_ltss_intr_r(),
+                                ltc_intr);
+}
+
+
 void gv11b_init_ltc(struct gpu_ops *gops)
 {
         gp10b_init_ltc(gops);
         gops->ltc.set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry;
+        gops->ltc.init_fs_state = gv11b_ltc_init_fs_state;
 }