diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-05-24 16:27:28 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-06-01 17:13:23 -0400 |
commit | 39727398230bdb0fb01d9aa54e4cc572f6d39299 (patch) | |
tree | 3cd3894d40ca83a58f5ba387eee1ea01d9c049c0 /drivers/gpu/nvgpu/gv11b | |
parent | d8d81ebda9af98fa0d9ff3b31d417867efcc4b2b (diff) |
gpu: nvgpu: gv11b: No need to set init val for fb & pbdma timeout
fb_timeout and pbdma_timeout values are already set by h/w to init
values. No need to reinitialize.
JIRA GPUT19X-22
Change-Id: If6f1111f58940d51e53f028b046c42fa852221ee
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1493458
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 15 |
1 files changed, 5 insertions, 10 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 38a402dc..b6691db5 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | |||
@@ -25,6 +25,7 @@ | |||
25 | #include <nvgpu/dma.h> | 25 | #include <nvgpu/dma.h> |
26 | #include <nvgpu/nvgpu_mem.h> | 26 | #include <nvgpu/nvgpu_mem.h> |
27 | #include <nvgpu/gmmu.h> | 27 | #include <nvgpu/gmmu.h> |
28 | #include <nvgpu/soc.h> | ||
28 | 29 | ||
29 | #include "gk20a/gk20a.h" | 30 | #include "gk20a/gk20a.h" |
30 | #include "gk20a/fifo_gk20a.h" | 31 | #include "gk20a/fifo_gk20a.h" |
@@ -1122,19 +1123,13 @@ static int gv11b_init_fifo_reset_enable_hw(struct gk20a *g) | |||
1122 | 1123 | ||
1123 | 1124 | ||
1124 | timeout = gk20a_readl(g, fifo_fb_timeout_r()); | 1125 | timeout = gk20a_readl(g, fifo_fb_timeout_r()); |
1125 | timeout = set_field(timeout, fifo_fb_timeout_period_m(), | 1126 | nvgpu_log_info(g, "fifo_fb_timeout reg val = 0x%08x", timeout); |
1126 | fifo_fb_timeout_period_init_f()); | ||
1127 | gk20a_dbg_info("fifo_fb_timeout reg val = 0x%08x", timeout); | ||
1128 | gk20a_writel(g, fifo_fb_timeout_r(), timeout); | ||
1129 | |||
1130 | /* write pbdma timeout value */ | ||
1131 | for (i = 0; i < host_num_pbdma; i++) { | 1127 | for (i = 0; i < host_num_pbdma; i++) { |
1132 | timeout = gk20a_readl(g, pbdma_timeout_r(i)); | 1128 | timeout = gk20a_readl(g, pbdma_timeout_r(i)); |
1133 | timeout = set_field(timeout, pbdma_timeout_period_m(), | 1129 | nvgpu_log_info(g, "pbdma_timeout reg val = 0x%08x", |
1134 | pbdma_timeout_period_init_f()); | 1130 | timeout); |
1135 | gk20a_dbg_info("pbdma_timeout reg val = 0x%08x", timeout); | ||
1136 | gk20a_writel(g, pbdma_timeout_r(i), timeout); | ||
1137 | } | 1131 | } |
1132 | |||
1138 | /* clear and enable pbdma interrupt */ | 1133 | /* clear and enable pbdma interrupt */ |
1139 | for (i = 0; i < host_num_pbdma; i++) { | 1134 | for (i = 0; i < host_num_pbdma; i++) { |
1140 | gk20a_writel(g, pbdma_intr_0_r(i), 0xFFFFFFFF); | 1135 | gk20a_writel(g, pbdma_intr_0_r(i), 0xFFFFFFFF); |