diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-07-02 18:31:03 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-07-05 06:06:53 -0400 |
commit | 30dcb317077a6a1651b856be56f714fb6016e21f (patch) | |
tree | 38450f9d3104f82ca4cdbc9068f8302a26db941e /drivers/gpu/nvgpu/gv11b | |
parent | edf87a42c3b18c2db8df07705ac26addc8c84df2 (diff) |
gpu: nvgpu: gv11b: init suspend_single_sm gr ops
Take care of SM register address changes.
JIRA GPUT19X-75
Change-Id: I7fa68dbef014fb07a3656b2816d7d8d538a7cf52
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1512207
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 40 |
1 files changed, 39 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 8e1f3af3..4f17a33c 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -1780,7 +1780,8 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, | |||
1780 | "CILP: STOP_TRIGGER from " | 1780 | "CILP: STOP_TRIGGER from " |
1781 | "gpc %d tpc %d sm %d", | 1781 | "gpc %d tpc %d sm %d", |
1782 | gpc, tpc, sm); | 1782 | gpc, tpc, sm); |
1783 | gk20a_suspend_single_sm(g, gpc, tpc, global_mask, true); | 1783 | g->ops.gr.suspend_single_sm(g, |
1784 | gpc, tpc, sm, global_mask, true); | ||
1784 | } | 1785 | } |
1785 | 1786 | ||
1786 | /* reset the HWW errors after locking down */ | 1787 | /* reset the HWW errors after locking down */ |
@@ -2761,6 +2762,42 @@ static bool gv11b_gr_sm_debugger_attached(struct gk20a *g) | |||
2761 | return false; | 2762 | return false; |
2762 | } | 2763 | } |
2763 | 2764 | ||
2765 | static void gv11b_gr_suspend_single_sm(struct gk20a *g, | ||
2766 | u32 gpc, u32 tpc, u32 sm, | ||
2767 | u32 global_esr_mask, bool check_errors) | ||
2768 | { | ||
2769 | int err; | ||
2770 | u32 dbgr_control0; | ||
2771 | u32 offset = gk20a_gr_gpc_offset(g, gpc) + | ||
2772 | gk20a_gr_tpc_offset(g, tpc) + | ||
2773 | gv11b_gr_sm_offset(g, sm); | ||
2774 | |||
2775 | /* if an SM debugger isn't attached, skip suspend */ | ||
2776 | if (!g->ops.gr.sm_debugger_attached(g)) { | ||
2777 | nvgpu_err(g, | ||
2778 | "SM debugger not attached, skipping suspend!"); | ||
2779 | return; | ||
2780 | } | ||
2781 | |||
2782 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, | ||
2783 | "suspending gpc:%d, tpc:%d, sm%d", gpc, tpc, sm); | ||
2784 | |||
2785 | /* assert stop trigger. */ | ||
2786 | dbgr_control0 = gk20a_readl(g, | ||
2787 | gr_gpc0_tpc0_sm0_dbgr_control0_r() + offset); | ||
2788 | dbgr_control0 |= gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_enable_f(); | ||
2789 | gk20a_writel(g, gr_gpc0_tpc0_sm0_dbgr_control0_r() + offset, | ||
2790 | dbgr_control0); | ||
2791 | |||
2792 | err = gk20a_gr_wait_for_sm_lock_down(g, gpc, tpc, | ||
2793 | global_esr_mask, check_errors); | ||
2794 | if (err) { | ||
2795 | nvgpu_err(g, | ||
2796 | "SuspendSm failed"); | ||
2797 | return; | ||
2798 | } | ||
2799 | } | ||
2800 | |||
2764 | void gv11b_init_gr(struct gpu_ops *gops) | 2801 | void gv11b_init_gr(struct gpu_ops *gops) |
2765 | { | 2802 | { |
2766 | gp10b_init_gr(gops); | 2803 | gp10b_init_gr(gops); |
@@ -2830,4 +2867,5 @@ void gv11b_init_gr(struct gpu_ops *gops) | |||
2830 | gops->gr.record_sm_error_state = gv11b_gr_record_sm_error_state; | 2867 | gops->gr.record_sm_error_state = gv11b_gr_record_sm_error_state; |
2831 | gops->gr.set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask; | 2868 | gops->gr.set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask; |
2832 | gops->gr.sm_debugger_attached = gv11b_gr_sm_debugger_attached; | 2869 | gops->gr.sm_debugger_attached = gv11b_gr_sm_debugger_attached; |
2870 | gops->gr.suspend_single_sm = gv11b_gr_suspend_single_sm; | ||
2833 | } | 2871 | } |