summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/gv11b
diff options
context:
space:
mode:
authorTerje Bergstrom <tbergstrom@nvidia.com>2018-08-10 17:09:36 -0400
committerBo Yan <byan@nvidia.com>2018-08-20 14:00:59 -0400
commit227c6f7b7a499dd58e0db6859736cfe586ef0897 (patch)
treed354f8422647021693aefefa5124d865c29ecd32 /drivers/gpu/nvgpu/gv11b
parent9e69e0cf978b53706f55ffb873e3966b4bb3a7a8 (diff)
gpu: nvgpu: Move fuse HAL to common
Move implementation of fuse HAL to common/fuse. Also implements new fuse query functions for FBIO, FBP, TPC floorsweeping and security fuses. JIRA NVGPU-957 Change-Id: I55e256a4f1b59d50a721d4942907f70dc57467c4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1797177
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b')
-rw-r--r--drivers/gpu/nvgpu/gv11b/gr_gv11b.c7
-rw-r--r--drivers/gpu/nvgpu/gv11b/hal_gv11b.c16
2 files changed, 16 insertions, 7 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index 41d2f695..5d237839 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -59,7 +59,6 @@
59#include <nvgpu/hw/gv11b/hw_ram_gv11b.h> 59#include <nvgpu/hw/gv11b/hw_ram_gv11b.h>
60#include <nvgpu/hw/gv11b/hw_pbdma_gv11b.h> 60#include <nvgpu/hw/gv11b/hw_pbdma_gv11b.h>
61#include <nvgpu/hw/gv11b/hw_perf_gv11b.h> 61#include <nvgpu/hw/gv11b/hw_perf_gv11b.h>
62#include <nvgpu/hw/gv11b/hw_fuse_gv11b.h>
63 62
64#define GFXP_WFI_TIMEOUT_COUNT_IN_USEC_DEFAULT 100 63#define GFXP_WFI_TIMEOUT_COUNT_IN_USEC_DEFAULT 100
65 64
@@ -131,16 +130,16 @@ bool gr_gv11b_is_valid_gfx_class(struct gk20a *g, u32 class_num)
131 130
132void gr_gv11b_powergate_tpc(struct gk20a *g) 131void gr_gv11b_powergate_tpc(struct gk20a *g)
133{ 132{
134 u32 tpc_pg_status = gk20a_readl(g, fuse_status_opt_tpc_gpc_r(0)); 133 u32 tpc_pg_status = g->ops.fuse.fuse_status_opt_tpc_gpc(g, 0);
135 134
136 if (tpc_pg_status == g->tpc_pg_mask) { 135 if (tpc_pg_status == g->tpc_pg_mask) {
137 return; 136 return;
138 } 137 }
139 138
140 gk20a_writel(g, fuse_ctrl_opt_tpc_gpc_r(0), (g->tpc_pg_mask)); 139 g->ops.fuse.fuse_ctrl_opt_tpc_gpc(g, 0, g->tpc_pg_mask);
141 140
142 do { 141 do {
143 tpc_pg_status = gk20a_readl(g, fuse_status_opt_tpc_gpc_r(0)); 142 tpc_pg_status = g->ops.fuse.fuse_status_opt_tpc_gpc(g, 0);
144 } while (tpc_pg_status != g->tpc_pg_mask); 143 } while (tpc_pg_status != g->tpc_pg_mask);
145 144
146 gk20a_writel(g, gr_fe_tpc_pesmask_r(), gr_fe_tpc_pesmask_req_send_f() | 145 gk20a_writel(g, gr_fe_tpc_pesmask_r(), gr_fe_tpc_pesmask_req_send_f() |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index baafa801..0989e00a 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -39,6 +39,8 @@
39#include "common/ltc/ltc_gm20b.h" 39#include "common/ltc/ltc_gm20b.h"
40#include "common/ltc/ltc_gp10b.h" 40#include "common/ltc/ltc_gp10b.h"
41#include "common/ltc/ltc_gv11b.h" 41#include "common/ltc/ltc_gv11b.h"
42#include "common/fuse/fuse_gm20b.h"
43#include "common/fuse/fuse_gp10b.h"
42 44
43#include "gk20a/gk20a.h" 45#include "gk20a/gk20a.h"
44#include "gk20a/fifo_gk20a.h" 46#include "gk20a/fifo_gk20a.h"
@@ -65,7 +67,6 @@
65#include "gp10b/mm_gp10b.h" 67#include "gp10b/mm_gp10b.h"
66#include "gp10b/pmu_gp10b.h" 68#include "gp10b/pmu_gp10b.h"
67#include "gp10b/gr_gp10b.h" 69#include "gp10b/gr_gp10b.h"
68#include "gp10b/fuse_gp10b.h"
69 70
70#include "gp106/pmu_gp106.h" 71#include "gp106/pmu_gp106.h"
71#include "gp106/acr_gp106.h" 72#include "gp106/acr_gp106.h"
@@ -100,7 +101,6 @@
100#include <nvgpu/hw/gv11b/hw_ram_gv11b.h> 101#include <nvgpu/hw/gv11b/hw_ram_gv11b.h>
101#include <nvgpu/hw/gv11b/hw_top_gv11b.h> 102#include <nvgpu/hw/gv11b/hw_top_gv11b.h>
102#include <nvgpu/hw/gv11b/hw_pwr_gv11b.h> 103#include <nvgpu/hw/gv11b/hw_pwr_gv11b.h>
103#include <nvgpu/hw/gv11b/hw_fuse_gv11b.h>
104#include <nvgpu/hw/gv11b/hw_gr_gv11b.h> 104#include <nvgpu/hw/gv11b/hw_gr_gv11b.h>
105 105
106int gv11b_get_litter_value(struct gk20a *g, int value) 106int gv11b_get_litter_value(struct gk20a *g, int value)
@@ -689,7 +689,7 @@ static const struct gpu_ops gv11b_ops = {
689 .pmu_pg_init_param = gv11b_pg_gr_init, 689 .pmu_pg_init_param = gv11b_pg_gr_init,
690 .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list, 690 .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list,
691 .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list, 691 .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list,
692 .dump_secure_fuses = pmu_dump_security_fuses_gp10b, 692 .dump_secure_fuses = pmu_dump_security_fuses_gm20b,
693 .reset_engine = gp106_pmu_engine_reset, 693 .reset_engine = gp106_pmu_engine_reset,
694 .is_engine_in_reset = gp106_pmu_is_engine_in_reset, 694 .is_engine_in_reset = gp106_pmu_is_engine_in_reset,
695 .pmu_nsbootstrap = gv11b_pmu_bootstrap, 695 .pmu_nsbootstrap = gv11b_pmu_bootstrap,
@@ -801,6 +801,16 @@ static const struct gpu_ops gv11b_ops = {
801 .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable, 801 .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable,
802 .is_opt_feature_override_disable = 802 .is_opt_feature_override_disable =
803 gp10b_fuse_is_opt_feature_override_disable, 803 gp10b_fuse_is_opt_feature_override_disable,
804 .fuse_status_opt_fbio = gm20b_fuse_status_opt_fbio,
805 .fuse_status_opt_fbp = gm20b_fuse_status_opt_fbp,
806 .fuse_status_opt_rop_l2_fbp = gm20b_fuse_status_opt_rop_l2_fbp,
807 .fuse_status_opt_tpc_gpc = gm20b_fuse_status_opt_tpc_gpc,
808 .fuse_ctrl_opt_tpc_gpc = gm20b_fuse_ctrl_opt_tpc_gpc,
809 .fuse_opt_sec_debug_en = gm20b_fuse_opt_sec_debug_en,
810 .fuse_opt_priv_sec_en = gm20b_fuse_opt_priv_sec_en,
811 .read_vin_cal_fuse_rev = NULL,
812 .read_vin_cal_slope_intercept_fuse = NULL,
813 .read_vin_cal_gain_offset_fuse = NULL,
804 }, 814 },
805 .chip_init_gpu_characteristics = gv11b_init_gpu_characteristics, 815 .chip_init_gpu_characteristics = gv11b_init_gpu_characteristics,
806 .get_litter_value = gv11b_get_litter_value, 816 .get_litter_value = gv11b_get_litter_value,