diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-06-09 19:19:17 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-06-13 12:14:02 -0400 |
commit | 12a8f51aa7a056d070861b120fc945d946bc10f9 (patch) | |
tree | 4da7343d4b4a348130acabe62e3c264aefa63509 /drivers/gpu/nvgpu/gv11b | |
parent | 4f0e19d44dee9039378bce7bd0cfb11f36fd8926 (diff) |
gpu: nvgpu: gv11b: disable skedcheck18_l1_config_too_small
SKED_HWW_ESR_EN_SKEDCHECK18_L1_CONFIG_TOO_SMALL disabled
Bug 200315442
Change-Id: I6d5c5f2fe6255d480350e01959c3c340579646e2
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1499568
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index a703e72c..542ed1ff 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -285,6 +285,27 @@ static int gr_gv11b_handle_lrf_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
285 | 285 | ||
286 | } | 286 | } |
287 | 287 | ||
288 | static void gr_gv11b_enable_hww_exceptions(struct gk20a *g) | ||
289 | { | ||
290 | u32 val; | ||
291 | |||
292 | /* enable exceptions */ | ||
293 | gk20a_writel(g, gr_fe_hww_esr_r(), | ||
294 | gr_fe_hww_esr_en_enable_f() | | ||
295 | gr_fe_hww_esr_reset_active_f()); | ||
296 | gk20a_writel(g, gr_memfmt_hww_esr_r(), | ||
297 | gr_memfmt_hww_esr_en_enable_f() | | ||
298 | gr_memfmt_hww_esr_reset_active_f()); | ||
299 | /* WAR for 200315442 */ | ||
300 | val = gk20a_readl(g, gr_sked_hww_esr_en_r()); | ||
301 | val = set_field(val, | ||
302 | gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(), | ||
303 | gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f() | ||
304 | ); | ||
305 | nvgpu_log_info(g, "sked_hww_esr_en = 0x%x", val); | ||
306 | gk20a_writel(g, gr_sked_hww_esr_en_r(), val); | ||
307 | } | ||
308 | |||
288 | static void gr_gv11b_enable_exceptions(struct gk20a *g) | 309 | static void gr_gv11b_enable_exceptions(struct gk20a *g) |
289 | { | 310 | { |
290 | struct gr_gk20a *gr = &g->gr; | 311 | struct gr_gk20a *gr = &g->gr; |
@@ -2518,6 +2539,7 @@ void gv11b_init_gr(struct gpu_ops *gops) | |||
2518 | gops->gr.handle_tex_exception = gr_gv11b_handle_tex_exception; | 2539 | gops->gr.handle_tex_exception = gr_gv11b_handle_tex_exception; |
2519 | gops->gr.enable_gpc_exceptions = gr_gv11b_enable_gpc_exceptions; | 2540 | gops->gr.enable_gpc_exceptions = gr_gv11b_enable_gpc_exceptions; |
2520 | gops->gr.enable_exceptions = gr_gv11b_enable_exceptions; | 2541 | gops->gr.enable_exceptions = gr_gv11b_enable_exceptions; |
2542 | gops->gr.enable_hww_exceptions = gr_gv11b_enable_hww_exceptions; | ||
2521 | gops->gr.mask_hww_warp_esr = gv11b_mask_hww_warp_esr; | 2543 | gops->gr.mask_hww_warp_esr = gv11b_mask_hww_warp_esr; |
2522 | gops->gr.pre_process_sm_exception = | 2544 | gops->gr.pre_process_sm_exception = |
2523 | gr_gv11b_pre_process_sm_exception; | 2545 | gr_gv11b_pre_process_sm_exception; |