diff options
author | Alex Waterman <alexw@nvidia.com> | 2017-10-06 20:20:12 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-10-24 18:16:49 -0400 |
commit | 0899e11d4bb630381607a0c245f72476e2e9209e (patch) | |
tree | 9ac90c2629e30d9c9e3f8c237f45eab6cd9f386f /drivers/gpu/nvgpu/gv11b | |
parent | df4e88a21d51d5e098b66c3094fa91ae633777e5 (diff) |
gpu: nvgpu: Cleanup generic MM code
t19x changes necessary for change in core MM code.
JIRA NVGPU-30
Change-Id: I62f419450c1a33d0826390d7cbb5ad93569f8c89
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1577265
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/acr_gv11b.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/css_gr_gv11b.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/dbg_gpu_gv11b.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 3 |
7 files changed, 14 insertions, 12 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/acr_gv11b.c b/drivers/gpu/nvgpu/gv11b/acr_gv11b.c index e2454f85..b245dbc6 100644 --- a/drivers/gpu/nvgpu/gv11b/acr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/acr_gv11b.c | |||
@@ -35,6 +35,7 @@ | |||
35 | #include <nvgpu/nvgpu_mem.h> | 35 | #include <nvgpu/nvgpu_mem.h> |
36 | #include <nvgpu/acr/nvgpu_acr.h> | 36 | #include <nvgpu/acr/nvgpu_acr.h> |
37 | #include <nvgpu/firmware.h> | 37 | #include <nvgpu/firmware.h> |
38 | #include <nvgpu/mm.h> | ||
38 | 39 | ||
39 | #include "gk20a/gk20a.h" | 40 | #include "gk20a/gk20a.h" |
40 | #include "acr_gv11b.h" | 41 | #include "acr_gv11b.h" |
@@ -211,7 +212,7 @@ static int bl_bootstrap(struct nvgpu_pmu *pmu, | |||
211 | pwr_falcon_itfen_ctxen_enable_f()); | 212 | pwr_falcon_itfen_ctxen_enable_f()); |
212 | gk20a_writel(g, pwr_pmu_new_instblk_r(), | 213 | gk20a_writel(g, pwr_pmu_new_instblk_r(), |
213 | pwr_pmu_new_instblk_ptr_f( | 214 | pwr_pmu_new_instblk_ptr_f( |
214 | gk20a_mm_inst_block_addr(g, &mm->pmu.inst_block) >> 12) | | 215 | nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> 12) | |
215 | pwr_pmu_new_instblk_valid_f(1) | | 216 | pwr_pmu_new_instblk_valid_f(1) | |
216 | pwr_pmu_new_instblk_target_sys_ncoh_f()); | 217 | pwr_pmu_new_instblk_target_sys_ncoh_f()); |
217 | 218 | ||
@@ -291,4 +292,3 @@ int gv11b_init_pmu_setup_hw1(struct gk20a *g, | |||
291 | return err; | 292 | return err; |
292 | return 0; | 293 | return 0; |
293 | } | 294 | } |
294 | |||
diff --git a/drivers/gpu/nvgpu/gv11b/css_gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/css_gr_gv11b.c index 6afd92fa..bf3383fd 100644 --- a/drivers/gpu/nvgpu/gv11b/css_gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/css_gr_gv11b.c | |||
@@ -135,8 +135,7 @@ int gv11b_css_hw_enable_snapshot(struct channel_gk20a *ch, | |||
135 | gk20a_writel(g, perf_pmasys_outsize_r(), snapshot_size); | 135 | gk20a_writel(g, perf_pmasys_outsize_r(), snapshot_size); |
136 | 136 | ||
137 | /* this field is aligned to 4K */ | 137 | /* this field is aligned to 4K */ |
138 | inst_pa_page = gk20a_mm_inst_block_addr(g, | 138 | inst_pa_page = nvgpu_inst_block_addr(g, &g->mm.hwpm.inst_block) >> 12; |
139 | &g->mm.hwpm.inst_block) >> 12; | ||
140 | 139 | ||
141 | gk20a_writel(g, perf_pmasys_mem_block_r(), | 140 | gk20a_writel(g, perf_pmasys_mem_block_r(), |
142 | perf_pmasys_mem_block_base_f(inst_pa_page) | | 141 | perf_pmasys_mem_block_base_f(inst_pa_page) | |
diff --git a/drivers/gpu/nvgpu/gv11b/dbg_gpu_gv11b.c b/drivers/gpu/nvgpu/gv11b/dbg_gpu_gv11b.c index 2fdfc8f4..a02c2ddd 100644 --- a/drivers/gpu/nvgpu/gv11b/dbg_gpu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/dbg_gpu_gv11b.c | |||
@@ -58,8 +58,7 @@ int gv11b_perfbuf_enable_locked(struct gk20a *g, u64 offset, u32 size) | |||
58 | gk20a_writel(g, perf_pmasys_outsize_r(), size); | 58 | gk20a_writel(g, perf_pmasys_outsize_r(), size); |
59 | 59 | ||
60 | /* this field is aligned to 4K */ | 60 | /* this field is aligned to 4K */ |
61 | inst_pa_page = gk20a_mm_inst_block_addr(g, | 61 | inst_pa_page = nvgpu_inst_block_addr(g, &mm->perfbuf.inst_block) >> 12; |
62 | &mm->perfbuf.inst_block) >> 12; | ||
63 | 62 | ||
64 | gk20a_writel(g, perf_pmasys_mem_block_r(), | 63 | gk20a_writel(g, perf_pmasys_mem_block_r(), |
65 | perf_pmasys_mem_block_base_f(inst_pa_page) | | 64 | perf_pmasys_mem_block_base_f(inst_pa_page) | |
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 4a03e6d9..dc3b641a 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | |||
@@ -34,6 +34,7 @@ | |||
34 | #include <nvgpu/debug.h> | 34 | #include <nvgpu/debug.h> |
35 | #include <nvgpu/nvhost_t19x.h> | 35 | #include <nvgpu/nvhost_t19x.h> |
36 | #include <nvgpu/barrier.h> | 36 | #include <nvgpu/barrier.h> |
37 | #include <nvgpu/mm.h> | ||
37 | 38 | ||
38 | #include "gk20a/gk20a.h" | 39 | #include "gk20a/gk20a.h" |
39 | #include "gk20a/fifo_gk20a.h" | 40 | #include "gk20a/fifo_gk20a.h" |
@@ -112,9 +113,9 @@ void gv11b_get_ch_runlist_entry(struct channel_gk20a *c, u32 *runlist) | |||
112 | runlist[0] = runlist_entry | ram_rl_entry_chan_userd_ptr_lo_f(addr_lo); | 113 | runlist[0] = runlist_entry | ram_rl_entry_chan_userd_ptr_lo_f(addr_lo); |
113 | runlist[1] = ram_rl_entry_chan_userd_ptr_hi_f(addr_hi); | 114 | runlist[1] = ram_rl_entry_chan_userd_ptr_hi_f(addr_hi); |
114 | 115 | ||
115 | addr_lo = u64_lo32(gk20a_mm_inst_block_addr(g, &c->inst_block)) >> | 116 | addr_lo = u64_lo32(nvgpu_inst_block_addr(g, &c->inst_block)) >> |
116 | ram_rl_entry_chan_inst_ptr_align_shift_v(); | 117 | ram_rl_entry_chan_inst_ptr_align_shift_v(); |
117 | addr_hi = u64_hi32(gk20a_mm_inst_block_addr(g, &c->inst_block)); | 118 | addr_hi = u64_hi32(nvgpu_inst_block_addr(g, &c->inst_block)); |
118 | 119 | ||
119 | runlist[2] = ram_rl_entry_chan_inst_ptr_lo_f(addr_lo) | | 120 | runlist[2] = ram_rl_entry_chan_inst_ptr_lo_f(addr_lo) | |
120 | ram_rl_entry_chid_f(c->chid); | 121 | ram_rl_entry_chid_f(c->chid); |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 5b10b7d2..46323cf9 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -549,6 +549,7 @@ static const struct gpu_ops gv11b_ops = { | |||
549 | .init_pdb = gp10b_mm_init_pdb, | 549 | .init_pdb = gp10b_mm_init_pdb, |
550 | .init_mm_setup_hw = gv11b_init_mm_setup_hw, | 550 | .init_mm_setup_hw = gv11b_init_mm_setup_hw, |
551 | .is_bar1_supported = gv11b_mm_is_bar1_supported, | 551 | .is_bar1_supported = gv11b_mm_is_bar1_supported, |
552 | .alloc_inst_block = gk20a_alloc_inst_block, | ||
552 | .init_inst_block = gv11b_init_inst_block, | 553 | .init_inst_block = gv11b_init_inst_block, |
553 | .mmu_fault_pending = gv11b_mm_mmu_fault_pending, | 554 | .mmu_fault_pending = gv11b_mm_mmu_fault_pending, |
554 | .get_kind_invalid = gm20b_get_kind_invalid, | 555 | .get_kind_invalid = gm20b_get_kind_invalid, |
diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index 6df29cb0..fdc506ac 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c | |||
@@ -27,6 +27,7 @@ | |||
27 | #include <nvgpu/kmem.h> | 27 | #include <nvgpu/kmem.h> |
28 | #include <nvgpu/dma.h> | 28 | #include <nvgpu/dma.h> |
29 | #include <nvgpu/log.h> | 29 | #include <nvgpu/log.h> |
30 | #include <nvgpu/mm.h> | ||
30 | 31 | ||
31 | #include "gk20a/gk20a.h" | 32 | #include "gk20a/gk20a.h" |
32 | #include "gk20a/mm_gk20a.h" | 33 | #include "gk20a/mm_gk20a.h" |
@@ -54,7 +55,7 @@ void gv11b_init_inst_block(struct nvgpu_mem *inst_block, | |||
54 | struct gk20a *g = gk20a_from_vm(vm); | 55 | struct gk20a *g = gk20a_from_vm(vm); |
55 | 56 | ||
56 | gk20a_dbg_info("inst block phys = 0x%llx, kv = 0x%p", | 57 | gk20a_dbg_info("inst block phys = 0x%llx, kv = 0x%p", |
57 | gk20a_mm_inst_block_addr(g, inst_block), inst_block->cpu_va); | 58 | nvgpu_inst_block_addr(g, inst_block), inst_block->cpu_va); |
58 | 59 | ||
59 | g->ops.mm.init_pdb(g, inst_block, vm); | 60 | g->ops.mm.init_pdb(g, inst_block, vm); |
60 | 61 | ||
@@ -191,7 +192,7 @@ void gv11b_mm_remove_bar2_vm(struct gk20a *g) | |||
191 | 192 | ||
192 | gv11b_mm_mmu_hw_fault_buf_deinit(g); | 193 | gv11b_mm_mmu_hw_fault_buf_deinit(g); |
193 | 194 | ||
194 | gk20a_free_inst_block(g, &mm->bar2.inst_block); | 195 | nvgpu_free_inst_block(g, &mm->bar2.inst_block); |
195 | nvgpu_vm_put(mm->bar2.vm); | 196 | nvgpu_vm_put(mm->bar2.vm); |
196 | } | 197 | } |
197 | 198 | ||
@@ -282,7 +283,7 @@ int gv11b_init_bar2_mm_hw_setup(struct gk20a *g) | |||
282 | { | 283 | { |
283 | struct mm_gk20a *mm = &g->mm; | 284 | struct mm_gk20a *mm = &g->mm; |
284 | struct nvgpu_mem *inst_block = &mm->bar2.inst_block; | 285 | struct nvgpu_mem *inst_block = &mm->bar2.inst_block; |
285 | u64 inst_pa = gk20a_mm_inst_block_addr(g, inst_block); | 286 | u64 inst_pa = nvgpu_inst_block_addr(g, inst_block); |
286 | u32 reg_val; | 287 | u32 reg_val; |
287 | struct nvgpu_timeout timeout; | 288 | struct nvgpu_timeout timeout; |
288 | u32 delay = GR_IDLE_CHECK_DEFAULT; | 289 | u32 delay = GR_IDLE_CHECK_DEFAULT; |
diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 74ed9165..2c7b6457 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | |||
@@ -30,6 +30,7 @@ | |||
30 | #include <nvgpu/pmu.h> | 30 | #include <nvgpu/pmu.h> |
31 | #include <nvgpu/falcon.h> | 31 | #include <nvgpu/falcon.h> |
32 | #include <nvgpu/enabled.h> | 32 | #include <nvgpu/enabled.h> |
33 | #include <nvgpu/mm.h> | ||
33 | 34 | ||
34 | #include "gk20a/gk20a.h" | 35 | #include "gk20a/gk20a.h" |
35 | 36 | ||
@@ -104,7 +105,7 @@ int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu) | |||
104 | 105 | ||
105 | gk20a_writel(g, pwr_pmu_new_instblk_r(), | 106 | gk20a_writel(g, pwr_pmu_new_instblk_r(), |
106 | pwr_pmu_new_instblk_ptr_f( | 107 | pwr_pmu_new_instblk_ptr_f( |
107 | gk20a_mm_inst_block_addr(g, &mm->pmu.inst_block) >> ALIGN_4KB) | 108 | nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> ALIGN_4KB) |
108 | | pwr_pmu_new_instblk_valid_f(1) | 109 | | pwr_pmu_new_instblk_valid_f(1) |
109 | | pwr_pmu_new_instblk_target_sys_ncoh_f()); | 110 | | pwr_pmu_new_instblk_target_sys_ncoh_f()); |
110 | 111 | ||