diff options
author | Konsta Holtta <kholtta@nvidia.com> | 2018-06-25 08:47:15 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-06-28 14:13:35 -0400 |
commit | dd146d42fc910128b0e2987d12b83430bf97bae0 (patch) | |
tree | 23d3f808eb6ea65dd8ab90398a22ff52fce09736 /drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | |
parent | 2dda362e6395a6d486ba3d1a75e707933690023e (diff) |
gpu: nvgpu: don't mem_{begin,end}() for gr
Now that GR buffers always have a kernel mapping, remove the unnecessary
calls to nvgpu_mem_begin() and nvgpu_mem_end() on these buffers:
- global ctx buffer mem in gr
- gr ctx mem in a tsg
- patch ctx mem in a gr ctx
- pm ctx mem in a gr ctx
- ctx_header mem in a channel (subctx header)
Change-Id: Id2a8ad108aef8db8b16dce5bae8003bbcd3b23e4
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1760599
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/subctx_gv11b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 8 |
1 files changed, 1 insertions, 7 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index 61fb8954..aad2b2fc 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | |||
@@ -82,11 +82,7 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c) | |||
82 | return -ENOMEM; | 82 | return -ENOMEM; |
83 | } | 83 | } |
84 | /* Now clear the buffer */ | 84 | /* Now clear the buffer */ |
85 | if (nvgpu_mem_begin(g, &ctx->mem)) | ||
86 | return -ENOMEM; | ||
87 | |||
88 | nvgpu_memset(g, &ctx->mem, 0, 0, ctx->mem.size); | 85 | nvgpu_memset(g, &ctx->mem, 0, 0, ctx->mem.size); |
89 | nvgpu_mem_end(g, &ctx->mem); | ||
90 | } | 86 | } |
91 | return ret; | 87 | return ret; |
92 | } | 88 | } |
@@ -117,8 +113,6 @@ int gv11b_update_subctx_header(struct channel_gk20a *c, u64 gpu_va) | |||
117 | 113 | ||
118 | gr_mem = &ctx->mem; | 114 | gr_mem = &ctx->mem; |
119 | g->ops.mm.l2_flush(g, true); | 115 | g->ops.mm.l2_flush(g, true); |
120 | if (nvgpu_mem_begin(g, gr_mem)) | ||
121 | return -ENOMEM; | ||
122 | 116 | ||
123 | /* set priv access map */ | 117 | /* set priv access map */ |
124 | addr_lo = u64_lo32(gr_ctx->global_ctx_buffer_va[PRIV_ACCESS_MAP_VA]); | 118 | addr_lo = u64_lo32(gr_ctx->global_ctx_buffer_va[PRIV_ACCESS_MAP_VA]); |
@@ -153,7 +147,7 @@ int gv11b_update_subctx_header(struct channel_gk20a *c, u64 gpu_va) | |||
153 | nvgpu_mem_wr(g, gr_mem, | 147 | nvgpu_mem_wr(g, gr_mem, |
154 | ctxsw_prog_main_image_ctl_o(), | 148 | ctxsw_prog_main_image_ctl_o(), |
155 | ctxsw_prog_main_image_ctl_type_per_veid_header_v()); | 149 | ctxsw_prog_main_image_ctl_type_per_veid_header_v()); |
156 | nvgpu_mem_end(g, gr_mem); | 150 | |
157 | return ret; | 151 | return ret; |
158 | } | 152 | } |
159 | 153 | ||