gpu: nvgpu: Enable IO coherency on GV100

This reverts commit 848af2ce6de6140323a6ffe3075bf8021e119434.

This is a revert of a revert, etc, etc. It re-enables IO coherence again.

JIRA EVLR-2333

Change-Id: Ibf97dce2f892e48a1200a06cd38a1c5d9603be04
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1669722
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 3 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c
index 12a606bf..61fb8954 100644
--- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c
@@ -178,8 +178,9 @@ void gv11b_subctx_commit_pdb(struct vm_gk20a *vm,
         u64 pdb_addr;
         u32 max_subctx_count = gr_pri_fe_chip_def_info_max_veid_count_init_v();
         u32 aperture = nvgpu_aperture_mask(g, vm->pdb.mem,
-                        ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(),
-                        ram_in_sc_page_dir_base_target_vid_mem_v());
+                                ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(),
+                                ram_in_sc_page_dir_base_target_sys_mem_coh_v(),
+                                ram_in_sc_page_dir_base_target_vid_mem_v());
 
         pdb_addr = nvgpu_mem_get_addr(g, vm->pdb.mem);
         pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v());