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authorRichard Zhao <rizhao@nvidia.com>2017-08-10 19:34:16 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-08-11 14:08:41 -0400
commit3197a918d5052c71ad854f6b22fdb35bfe7cebe2 (patch)
tree887f155d104926d38d74583739bacf57a57c040b /drivers/gpu/nvgpu/gv11b/subctx_gv11b.c
parentde8e057f7eebcfe676278826ab457bf86b1b36fd (diff)
gpu: nvgpu: gv11b: add max_subctx_count to g->fifo.t19x
- For better performance. It used to read register every time referencing max_subctx_count. - Avoid reading registers for vgpu. Jira VFND-3797 Change-Id: Id6e6b15a0d9a035795e8a9a2c6bb63524c5eb544 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1537009 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/subctx_gv11b.c')
-rw-r--r--drivers/gpu/nvgpu/gv11b/subctx_gv11b.c13
1 files changed, 2 insertions, 11 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c
index 72a66530..4f64843c 100644
--- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c
@@ -26,7 +26,6 @@
26 26
27#include <nvgpu/hw/gv11b/hw_ram_gv11b.h> 27#include <nvgpu/hw/gv11b/hw_ram_gv11b.h>
28#include <nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h> 28#include <nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h>
29#include <nvgpu/hw/gv11b/hw_gr_gv11b.h>
30 29
31static void gv11b_init_subcontext_pdb(struct channel_gk20a *c, 30static void gv11b_init_subcontext_pdb(struct channel_gk20a *c,
32 struct nvgpu_mem *inst_block); 31 struct nvgpu_mem *inst_block);
@@ -143,6 +142,7 @@ void gv11b_subctx_commit_pdb(struct channel_gk20a *c,
143 struct nvgpu_mem *inst_block) 142 struct nvgpu_mem *inst_block)
144{ 143{
145 struct gk20a *g = c->g; 144 struct gk20a *g = c->g;
145 struct fifo_gk20a *f = &g->fifo;
146 struct vm_gk20a *vm = c->vm; 146 struct vm_gk20a *vm = c->vm;
147 u32 lo, hi; 147 u32 lo, hi;
148 u32 subctx_id = 0; 148 u32 subctx_id = 0;
@@ -164,19 +164,10 @@ void gv11b_subctx_commit_pdb(struct channel_gk20a *c,
164 ram_in_sc_page_dir_base_lo_0_f(pdb_addr_lo); 164 ram_in_sc_page_dir_base_lo_0_f(pdb_addr_lo);
165 nvgpu_log(g, gpu_dbg_info, " pdb info lo %x hi %x", 165 nvgpu_log(g, gpu_dbg_info, " pdb info lo %x hi %x",
166 format_word, pdb_addr_hi); 166 format_word, pdb_addr_hi);
167 for (subctx_id = 0; subctx_id < gv11b_get_max_subctx_count(g); 167 for (subctx_id = 0; subctx_id < f->t19x.max_subctx_count; subctx_id++) {
168 subctx_id++) {
169 lo = ram_in_sc_page_dir_base_vol_0_w() + (4 * subctx_id); 168 lo = ram_in_sc_page_dir_base_vol_0_w() + (4 * subctx_id);
170 hi = ram_in_sc_page_dir_base_hi_0_w() + (4 * subctx_id); 169 hi = ram_in_sc_page_dir_base_hi_0_w() + (4 * subctx_id);
171 nvgpu_mem_wr32(g, inst_block, lo, format_word); 170 nvgpu_mem_wr32(g, inst_block, lo, format_word);
172 nvgpu_mem_wr32(g, inst_block, hi, pdb_addr_hi); 171 nvgpu_mem_wr32(g, inst_block, hi, pdb_addr_hi);
173 } 172 }
174} 173}
175
176
177u32 gv11b_get_max_subctx_count(struct gk20a *g)
178{
179 u32 data = gk20a_readl(g, gr_pri_fe_chip_def_info_r());
180
181 return gr_pri_fe_chip_def_info_max_veid_count_v(data);
182}