gpu: nvgpu: gv11b, rename gk20a_pmu_cmd_post()

- replaced gk20a_pmu_cmd_post() with nvgpu_pmu_cmd_post()
wherever called.

JIRA NVGPU-93

Change-Id: I1ce20cdd7190311535917058ad09a8896e505179
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master/r/1512972
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>

1 files changed, 2 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c
index ecc77e1b..fe468f19 100644
--- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c
@@ -197,7 +197,7 @@ static int gv11b_pg_gr_init(struct gk20a *g, u32 pg_engine_id)
                                 PMU_PG_FEATURE_GR_POWER_GATING_ENABLED;
 
                 gv11b_dbg_pmu("cmd post PMU_PG_CMD_ID_PG_PARAM_INIT\n");
-                gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
+                nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
                                         pmu_handle_pg_param_msg, pmu, &seq, ~0);
 
         } else
@@ -227,7 +227,7 @@ static int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id)
                                 PMU_PG_FEATURE_GR_POWER_GATING_ENABLED;
 
                 gv11b_dbg_pmu("cmd post PMU_PG_CMD_SUB_FEATURE_MASK_UPDATE\n");
-                gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
+                nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
                                 pmu_handle_pg_sub_feature_msg, pmu, &seq, ~0);
         } else
                 return -EINVAL;