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authorTerje Bergstrom <tbergstrom@nvidia.com>2018-04-18 22:39:46 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-05-09 21:26:04 -0400
commitdd739fcb039d51606e9a5454ec0aab17bcb01965 (patch)
tree806ba8575d146367ad1be00086ca0cdae35a6b28 /drivers/gpu/nvgpu/gv11b/pmu_gv11b.c
parent7e66f2a63d4855e763fa768047dfc32f6f96b771 (diff)
gpu: nvgpu: Remove gk20a_dbg* functions
Switch all logging to nvgpu_log*(). gk20a_dbg* macros are intentionally left there because of use from other repositories. Because the new functions do not work without a pointer to struct gk20a, and piping it just for logging is excessive, some log messages are deleted. Change-Id: I00e22e75fe4596a330bb0282ab4774b3639ee31e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1704148 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/pmu_gv11b.c')
-rw-r--r--drivers/gpu/nvgpu/gv11b/pmu_gv11b.c22
1 files changed, 11 insertions, 11 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c
index c1b519d0..3f0e2f22 100644
--- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c
@@ -37,8 +37,8 @@
37 37
38#include <nvgpu/hw/gv11b/hw_pwr_gv11b.h> 38#include <nvgpu/hw/gv11b/hw_pwr_gv11b.h>
39 39
40#define gv11b_dbg_pmu(fmt, arg...) \ 40#define gv11b_dbg_pmu(g, fmt, arg...) \
41 gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) 41 nvgpu_log(g, gpu_dbg_pmu, fmt, ##arg)
42 42
43#define ALIGN_4KB 12 43#define ALIGN_4KB 12
44 44
@@ -121,7 +121,7 @@ int gv11b_pmu_setup_elpg(struct gk20a *g)
121 u32 reg_writes; 121 u32 reg_writes;
122 u32 index; 122 u32 index;
123 123
124 gk20a_dbg_fn(""); 124 nvgpu_log_fn(g, " ");
125 125
126 if (g->elpg_enabled) { 126 if (g->elpg_enabled) {
127 reg_writes = ((sizeof(_pginitseq_gv11b) / 127 reg_writes = ((sizeof(_pginitseq_gv11b) /
@@ -133,7 +133,7 @@ int gv11b_pmu_setup_elpg(struct gk20a *g)
133 } 133 }
134 } 134 }
135 135
136 gk20a_dbg_fn("done"); 136 nvgpu_log_fn(g, "done");
137 return ret; 137 return ret;
138} 138}
139 139
@@ -187,7 +187,7 @@ int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu)
187 u64 addr_code_hi, addr_data_hi; 187 u64 addr_code_hi, addr_data_hi;
188 u32 i, blocks, addr_args; 188 u32 i, blocks, addr_args;
189 189
190 gk20a_dbg_fn(""); 190 nvgpu_log_fn(g, " ");
191 191
192 gk20a_writel(g, pwr_falcon_itfen_r(), 192 gk20a_writel(g, pwr_falcon_itfen_r(),
193 gk20a_readl(g, pwr_falcon_itfen_r()) | 193 gk20a_readl(g, pwr_falcon_itfen_r()) |
@@ -407,28 +407,28 @@ u32 gv11b_pmu_get_irqdest(struct gk20a *g)
407static void pmu_handle_pg_sub_feature_msg(struct gk20a *g, struct pmu_msg *msg, 407static void pmu_handle_pg_sub_feature_msg(struct gk20a *g, struct pmu_msg *msg,
408 void *param, u32 handle, u32 status) 408 void *param, u32 handle, u32 status)
409{ 409{
410 gk20a_dbg_fn(""); 410 nvgpu_log_fn(g, " ");
411 411
412 if (status != 0) { 412 if (status != 0) {
413 nvgpu_err(g, "Sub-feature mask update cmd aborted\n"); 413 nvgpu_err(g, "Sub-feature mask update cmd aborted\n");
414 return; 414 return;
415 } 415 }
416 416
417 gv11b_dbg_pmu("sub-feature mask update is acknowledged from PMU %x\n", 417 gv11b_dbg_pmu(g, "sub-feature mask update is acknowledged from PMU %x\n",
418 msg->msg.pg.msg_type); 418 msg->msg.pg.msg_type);
419} 419}
420 420
421static void pmu_handle_pg_param_msg(struct gk20a *g, struct pmu_msg *msg, 421static void pmu_handle_pg_param_msg(struct gk20a *g, struct pmu_msg *msg,
422 void *param, u32 handle, u32 status) 422 void *param, u32 handle, u32 status)
423{ 423{
424 gk20a_dbg_fn(""); 424 nvgpu_log_fn(g, " ");
425 425
426 if (status != 0) { 426 if (status != 0) {
427 nvgpu_err(g, "GR PARAM cmd aborted\n"); 427 nvgpu_err(g, "GR PARAM cmd aborted\n");
428 return; 428 return;
429 } 429 }
430 430
431 gv11b_dbg_pmu("GR PARAM is acknowledged from PMU %x\n", 431 gv11b_dbg_pmu(g, "GR PARAM is acknowledged from PMU %x\n",
432 msg->msg.pg.msg_type); 432 msg->msg.pg.msg_type);
433} 433}
434 434
@@ -450,7 +450,7 @@ int gv11b_pg_gr_init(struct gk20a *g, u32 pg_engine_id)
450 cmd.cmd.pg.gr_init_param_v1.featuremask = 450 cmd.cmd.pg.gr_init_param_v1.featuremask =
451 NVGPU_PMU_GR_FEATURE_MASK_ALL; 451 NVGPU_PMU_GR_FEATURE_MASK_ALL;
452 452
453 gv11b_dbg_pmu("cmd post PMU_PG_CMD_ID_PG_PARAM_INIT\n"); 453 gv11b_dbg_pmu(g, "cmd post PMU_PG_CMD_ID_PG_PARAM_INIT\n");
454 nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, 454 nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
455 pmu_handle_pg_param_msg, pmu, &seq, ~0); 455 pmu_handle_pg_param_msg, pmu, &seq, ~0);
456 456
@@ -488,7 +488,7 @@ int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id)
488 NVGPU_PMU_GR_FEATURE_MASK_ELPG_LOGIC | 488 NVGPU_PMU_GR_FEATURE_MASK_ELPG_LOGIC |
489 NVGPU_PMU_GR_FEATURE_MASK_ELPG_L2RPPG; 489 NVGPU_PMU_GR_FEATURE_MASK_ELPG_L2RPPG;
490 490
491 gv11b_dbg_pmu("cmd post PMU_PG_CMD_SUB_FEATURE_MASK_UPDATE\n"); 491 gv11b_dbg_pmu(g, "cmd post PMU_PG_CMD_SUB_FEATURE_MASK_UPDATE\n");
492 nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, 492 nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
493 pmu_handle_pg_sub_feature_msg, pmu, &seq, ~0); 493 pmu_handle_pg_sub_feature_msg, pmu, &seq, ~0);
494 } else 494 } else