diff options
author | Timo Alho <talho@nvidia.com> | 2018-03-05 02:31:06 -0500 |
---|---|---|
committer | Timo Alho <talho@nvidia.com> | 2018-03-05 11:39:57 -0500 |
commit | 848af2ce6de6140323a6ffe3075bf8021e119434 (patch) | |
tree | c89f28ac819f637b554f191da2f6a0fd8d75253e /drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | |
parent | 89fbf39a05483917c0a9f3453fd94c724bc37375 (diff) |
Revert "Revert "Revert "gpu: nvgpu: Get coherency on gv100 + NVLINK working"""
This reverts commit 89fbf39a05483917c0a9f3453fd94c724bc37375.
Bug 2075315
Change-Id: Id34a0376be5160b164931926ec600f77edf69667
Signed-off-by: Timo Alho <talho@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1668487
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/pmu_gv11b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 13e70eca..7dd4f8f4 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | |||
@@ -195,11 +195,9 @@ int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu) | |||
195 | 195 | ||
196 | gk20a_writel(g, pwr_pmu_new_instblk_r(), | 196 | gk20a_writel(g, pwr_pmu_new_instblk_r(), |
197 | pwr_pmu_new_instblk_ptr_f( | 197 | pwr_pmu_new_instblk_ptr_f( |
198 | nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> ALIGN_4KB) | | 198 | nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> ALIGN_4KB) |
199 | pwr_pmu_new_instblk_valid_f(1) | | 199 | | pwr_pmu_new_instblk_valid_f(1) |
200 | (nvgpu_is_enabled(g, NVGPU_USE_COHERENT_SYSMEM) ? | 200 | | pwr_pmu_new_instblk_target_sys_ncoh_f()); |
201 | pwr_pmu_new_instblk_target_sys_coh_f() : | ||
202 | pwr_pmu_new_instblk_target_sys_ncoh_f())); | ||
203 | 201 | ||
204 | /* TBD: load all other surfaces */ | 202 | /* TBD: load all other surfaces */ |
205 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_size( | 203 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_size( |