gpu: nvgpu: Cleanup generic MM code

t19x changes necessary for change in core MM code.

JIRA NVGPU-30

Change-Id: I62f419450c1a33d0826390d7cbb5ad93569f8c89
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1577265
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 2 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c
index 74ed9165..2c7b6457 100644
--- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c
@@ -30,6 +30,7 @@
 #include <nvgpu/pmu.h>
 #include <nvgpu/falcon.h>
 #include <nvgpu/enabled.h>
+#include <nvgpu/mm.h>
 
 #include "gk20a/gk20a.h"
 
@@ -104,7 +105,7 @@ int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu)
 
         gk20a_writel(g, pwr_pmu_new_instblk_r(),
                 pwr_pmu_new_instblk_ptr_f(
-                gk20a_mm_inst_block_addr(g, &mm->pmu.inst_block) >> ALIGN_4KB)
+                nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> ALIGN_4KB)
                 | pwr_pmu_new_instblk_valid_f(1)
                 | pwr_pmu_new_instblk_target_sys_ncoh_f());