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| author | David Nieto <dmartineznie@nvidia.com> | 2017-05-05 17:22:06 -0400 |
|---|---|---|
| committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-05-11 09:04:33 -0400 |
| commit | 8c246cb18df28bac83297df2c9d0c47725b94273 (patch) | |
| tree | f0bc4bdd963b14ccafc9c888dd65d3485bb9bf5b /drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c | |
| parent | 44dcc5a53fabc68a32f16a1a3a46a2582b5b192b (diff) | |
gpu: nvgpu: gv11b: MMU parity HWW error intr
Adding support for ISR handling of ecc uncorrectable errors
for volta resiliency (Volta-686)
TODO: move interrupt init out of MC
bug 1881052
JIRA: GPUT19X-82
Change-Id: I45db01a6062445dd1f64a8297744cd15105e3344
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1476603
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c')
0 files changed, 0 insertions, 0 deletions