diff options
author | Sunny He <suhe@nvidia.com> | 2017-07-26 17:23:01 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-08-14 18:55:25 -0400 |
commit | 8ab6445df5b24c200ac4e346684119a85008e0e3 (patch) | |
tree | 557c0e126488532942c784bdfcdfe1e9bc6d2688 /drivers/gpu/nvgpu/gv11b/mm_gv11b.c | |
parent | 4bb0896912440d126ae47da350b448f37dabc63d (diff) |
gpu: nvgpu: Reorg mm HAL initialization
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
mm sub-module of the gpu_ops struct.
Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.
Jira NVGPU-74
Change-Id: I5fd295c6473d5b4a6178c0c6be8fcf8f4c33f2e3
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1537754
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/mm_gv11b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 32 |
1 files changed, 8 insertions, 24 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index 7ba8f74f..941a0bbe 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c | |||
@@ -34,12 +34,12 @@ | |||
34 | 34 | ||
35 | #define NVGPU_L3_ALLOC_BIT BIT(36) | 35 | #define NVGPU_L3_ALLOC_BIT BIT(36) |
36 | 36 | ||
37 | static bool gv11b_mm_is_bar1_supported(struct gk20a *g) | 37 | bool gv11b_mm_is_bar1_supported(struct gk20a *g) |
38 | { | 38 | { |
39 | return false; | 39 | return false; |
40 | } | 40 | } |
41 | 41 | ||
42 | static void gv11b_init_inst_block(struct nvgpu_mem *inst_block, | 42 | void gv11b_init_inst_block(struct nvgpu_mem *inst_block, |
43 | struct vm_gk20a *vm, u32 big_page_size) | 43 | struct vm_gk20a *vm, u32 big_page_size) |
44 | { | 44 | { |
45 | struct gk20a *g = gk20a_from_vm(vm); | 45 | struct gk20a *g = gk20a_from_vm(vm); |
@@ -53,12 +53,12 @@ static void gv11b_init_inst_block(struct nvgpu_mem *inst_block, | |||
53 | g->ops.mm.set_big_page_size(g, inst_block, big_page_size); | 53 | g->ops.mm.set_big_page_size(g, inst_block, big_page_size); |
54 | } | 54 | } |
55 | 55 | ||
56 | static bool gv11b_mm_mmu_fault_pending(struct gk20a *g) | 56 | bool gv11b_mm_mmu_fault_pending(struct gk20a *g) |
57 | { | 57 | { |
58 | return gv11b_fb_mmu_fault_pending(g); | 58 | return gv11b_fb_mmu_fault_pending(g); |
59 | } | 59 | } |
60 | 60 | ||
61 | static void gv11b_mm_fault_info_mem_destroy(struct gk20a *g) | 61 | void gv11b_mm_fault_info_mem_destroy(struct gk20a *g) |
62 | { | 62 | { |
63 | nvgpu_log_fn(g, " "); | 63 | nvgpu_log_fn(g, " "); |
64 | 64 | ||
@@ -174,7 +174,7 @@ static void gv11b_mm_mmu_hw_fault_buf_deinit(struct gk20a *g) | |||
174 | } | 174 | } |
175 | } | 175 | } |
176 | 176 | ||
177 | static void gv11b_mm_remove_bar2_vm(struct gk20a *g) | 177 | void gv11b_mm_remove_bar2_vm(struct gk20a *g) |
178 | { | 178 | { |
179 | struct mm_gk20a *mm = &g->mm; | 179 | struct mm_gk20a *mm = &g->mm; |
180 | 180 | ||
@@ -221,7 +221,7 @@ static int gv11b_mm_mmu_fault_setup_sw(struct gk20a *g) | |||
221 | return err; | 221 | return err; |
222 | } | 222 | } |
223 | 223 | ||
224 | static int gv11b_init_mm_setup_hw(struct gk20a *g) | 224 | int gv11b_init_mm_setup_hw(struct gk20a *g) |
225 | { | 225 | { |
226 | int err = 0; | 226 | int err = 0; |
227 | 227 | ||
@@ -260,7 +260,7 @@ void gv11b_mm_l2_flush(struct gk20a *g, bool invalidate) | |||
260 | * checking bit 36 of the phsyical address. So if a mapping should allocte lines | 260 | * checking bit 36 of the phsyical address. So if a mapping should allocte lines |
261 | * in the L3 this bit must be set. | 261 | * in the L3 this bit must be set. |
262 | */ | 262 | */ |
263 | static u64 gv11b_gpu_phys_addr(struct gk20a *g, | 263 | u64 gv11b_gpu_phys_addr(struct gk20a *g, |
264 | struct nvgpu_gmmu_attrs *attrs, u64 phys) | 264 | struct nvgpu_gmmu_attrs *attrs, u64 phys) |
265 | { | 265 | { |
266 | if (attrs && attrs->t19x_attrs.l3_alloc) | 266 | if (attrs && attrs->t19x_attrs.l3_alloc) |
@@ -269,7 +269,7 @@ static u64 gv11b_gpu_phys_addr(struct gk20a *g, | |||
269 | return phys; | 269 | return phys; |
270 | } | 270 | } |
271 | 271 | ||
272 | static int gv11b_init_bar2_mm_hw_setup(struct gk20a *g) | 272 | int gv11b_init_bar2_mm_hw_setup(struct gk20a *g) |
273 | { | 273 | { |
274 | struct mm_gk20a *mm = &g->mm; | 274 | struct mm_gk20a *mm = &g->mm; |
275 | struct nvgpu_mem *inst_block = &mm->bar2.inst_block; | 275 | struct nvgpu_mem *inst_block = &mm->bar2.inst_block; |
@@ -318,19 +318,3 @@ static int gv11b_init_bar2_mm_hw_setup(struct gk20a *g) | |||
318 | nvgpu_err(g, "bar2 bind failed. gpu unable to access memory"); | 318 | nvgpu_err(g, "bar2 bind failed. gpu unable to access memory"); |
319 | return -EBUSY; | 319 | return -EBUSY; |
320 | } | 320 | } |
321 | |||
322 | void gv11b_init_mm(struct gpu_ops *gops) | ||
323 | { | ||
324 | gp10b_init_mm(gops); | ||
325 | gops->mm.gpu_phys_addr = gv11b_gpu_phys_addr; | ||
326 | gops->mm.is_bar1_supported = gv11b_mm_is_bar1_supported; | ||
327 | gops->mm.init_inst_block = gv11b_init_inst_block; | ||
328 | gops->mm.mmu_fault_pending = gv11b_mm_mmu_fault_pending; | ||
329 | gops->mm.l2_flush = gv11b_mm_l2_flush; | ||
330 | gops->mm.gpu_phys_addr = gv11b_gpu_phys_addr; | ||
331 | gops->mm.init_mm_setup_hw = gv11b_init_mm_setup_hw; | ||
332 | gops->mm.fault_info_mem_destroy = | ||
333 | gv11b_mm_fault_info_mem_destroy; | ||
334 | gops->mm.remove_bar2_vm = gv11b_mm_remove_bar2_vm; | ||
335 | gops->mm.init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup; | ||
336 | } | ||