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| author | Lakshmanan M <lm@nvidia.com> | 2017-05-10 03:08:08 -0400 |
|---|---|---|
| committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-05-18 12:04:28 -0400 |
| commit | ffc37e50fa8e869e9a160b35f3cf414040e8a360 (patch) | |
| tree | 3b782fb489d10b52ab7ba12d8bbf7a6d10198ff9 /drivers/gpu/nvgpu/gv11b/mc_gv11b.h | |
| parent | 808af68d962b85594c2accd1069c6a2de35c50e4 (diff) | |
gpu: nvgpu: gv11b: Add L1 tags parity support
This CL covers the following parity support (corrected + uncorrected),
1) SM's L1 tags
2) SM's S2R's pixel PRF buffer
3) SM's L1 D-cache miss latency FIFOs
Volta Resiliency Id - Volta-720, Volta-721, Volta-637
JIRA GPUT19X-85
JIRA GPUT19X-104
JIRA GPUT19X-100
JIRA GPUT19X-103
Bug 1825948
Bug 1825962
Bug 1775457
Change-Id: I53d7231a36b2c7c252395eca27b349eca80dec63
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1478881
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/mc_gv11b.h')
0 files changed, 0 insertions, 0 deletions