gpu: nvgpu: Code updates for MISRA violations

Code related to MC module is updated for handling
MISRA violations

Rule 10.1: Operands shalln't be an inappropriate
essential type.
Rule 10.3: Value of expression shalln't be assigned
to an object with a narrow essential type.
Rule 10.4: Both operands in an operator shall have
the same essential type.
Rule 14.4: Controlling if statement shall have
essentially Boolean type.
Rule 15.6: Enclose if() sequences with braces.

JIRA NVGPU-646
JIRA NVGPU-659
JIRA NVGPU-671

Change-Id: Ia7ada40068eab5c164b8bad99bf8103b37a2fbc9
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1720926
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 9 insertions, 7 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c
index 74c5c4d6..6c118ceb 100644
--- a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c
@@ -1,7 +1,7 @@
 /*
  * GV11B master
  *
- * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -22,7 +22,7 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#include <linux/types.h>
+#include <nvgpu/types.h>
 
 #include "gk20a/gk20a.h"
 
@@ -38,9 +38,9 @@ void mc_gv11b_intr_enable(struct gk20a *g)
         u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g);
 
         gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING),
-                                0xffffffff);
+                                0xffffffffU);
         gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
-                                0xffffffff);
+                                0xffffffffU);
         gv11b_fb_disable_hub_intr(g, STALL_REG_INDEX, HUB_INTR_TYPE_ALL);
 
         g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] =
@@ -68,7 +68,7 @@ void mc_gv11b_intr_enable(struct gk20a *g)
 
 bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0)
 {
-        return ((mc_intr_0 & mc_intr_hub_pending_f()) ? true : false);
+        return (((mc_intr_0 & mc_intr_hub_pending_f()) != 0U) ? true : false);
 }
 
 bool gv11b_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id)
@@ -77,16 +77,18 @@ bool gv11b_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id)
         u32 stall_intr, eng_intr_mask;
 
         eng_intr_mask = gk20a_fifo_act_eng_interrupt_mask(g, act_eng_id);
-        if (mc_intr_0 & eng_intr_mask)
+        if ((mc_intr_0 & eng_intr_mask) != 0U) {
                 return true;
+        }
 
         stall_intr = mc_intr_pfifo_pending_f() |
                         mc_intr_hub_pending_f() |
                         mc_intr_priv_ring_pending_f() |
                         mc_intr_pbus_pending_f() |
                         mc_intr_ltc_pending_f();
-        if (mc_intr_0 & stall_intr)
+        if ((mc_intr_0 & stall_intr) != 0U) {
                 return true;
+        }
 
         return false;
 }