gpu: nvgpu: gv11b: set up for enabling/handling hub intr

-implement mm ops init_mm_setup_hw
 This will also call *fault*setup* that will do s/w and h/w
 set up required to get mmu fault info

-implement s/w set up for copying mmu faults
 Two shadow fault buffers are pre allocated which will be used to copy
 fault info. One for copying from fault snap registers/nonreplayable h/w
 fault buffers and one for replay h/w fault buffers

-implement s/w set up for buffering mmu faults
 Replayable/Non-replayable fault buffers are mapped in BAR2
 virtual/physical address space. These buffers are circular buffers in
 terms of address calculation. Currently there are num host channels
 buffers

-configure h/w for buffering mmu faults
 if s/w set up is successful, configure h/w registers to enable
 buffered mode of mmu faults

-if both s/w and h/w set up are successful, enable corresponding
 hub interrupts

-implement new ops, fault_info_buf_deinit
 This will be called during gk20a_mm_destroy to disable hub intr and
 de-allocate shadow fault buf that is used to copy mmu fault info during
 mmu fault handling

-implement mm ops remove_bar2_vm
 This will also unmap and free fault buffers mapped in BAR2 if fault
 buffers were allocated

JIRA GPUT19X-7
JIRA GPUT19X-12

Change-Id: I53a38eddbb0a50a1f2024600583f2aae1f1fba6d
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1492682
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit

1 files changed, 11 insertions, 8 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c
index 8b8fcea0..cc29f74a 100644
--- a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c
@@ -30,6 +30,10 @@ static void mc_gv11b_intr_enable(struct gk20a *g)
 
         gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING),
                                 0xffffffff);
+        gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
+                                0xffffffff);
+        gv11b_fb_disable_hub_intr(g, STALL_REG_INDEX, HUB_INTR_TYPE_ALL);
+
         g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] =
                                 mc_intr_pfifo_pending_f() |
                                 mc_intr_hub_pending_f() |
@@ -38,20 +42,19 @@ static void mc_gv11b_intr_enable(struct gk20a *g)
                                 mc_intr_ltc_pending_f() |
                                 eng_intr_mask;
 
-        gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
-                        g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]);
-
-        gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
-                                0xffffffff);
         g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] =
                                 mc_intr_pfifo_pending_f()
                              | eng_intr_mask;
+
+        /* TODO: Enable PRI faults for HUB ECC err intr */
+        gv11b_fb_enable_hub_intr(g, STALL_REG_INDEX, g->mm.hub_intr_types);
+
+        gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
+                        g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]);
+
         gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
                         g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
 
-        /* TODO: Enable PRI faults for HUB ECC err intr */
-        gv11b_fb_enable_hub_intr(g, STALL_REG_INDEX,
-                                                HUB_INTR_TYPE_ECC_UNCORRECTED);
 }
 
 static bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0)